Phase locked loop circuit

A method of controlling the phase relationship of at least two logic signals each having a periodic component of the same frequency, one of said logic signals having a pulse-duty factor different from 50:50 comprising the steps of:

• providing a control signal to means for regulating said phase relationship of said periodic components of said logic signals, said control signal having a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values;
• detecting if the state of said phase relationship of said components of said logic signals is locked;
• providing a third logic signal from a signal source, said third logic signal having a periodic component having the same frequency as said two logic signals and having a pulse width substantially wider than the pulse widths of said two logic signals;
• actuating a switch in response to detection of the state of said phase relationship of said components of said logic signals to apply said third logic signal to said control signal when said two logic signals are out-of-lock, whereby said control signal has said first value when said two logic signals are phase locked and said second value when one of said two logic signals and said third signal do not overlap.

A phase locked loop circuit comprising:

• a) a phase comparator, corresponding to the phase comparator of said loop, having first, second and third inputs, and an output;
• b) a source of input pulses coupled to said first input of said phase comparator;
• c) a controlled oscillator having a control input coupled to the output of said phase comparator, and an output coupled to said second input of said phase comparator;
• d) a switch;
• e) a source of pulses having a duration greater than the duration of said input pulses, said source being coupled to said third input of said phase comparator through said switch;
• and
• f) means for detecting the lock status of said phase locked loop, and for causing said switch to couple said source of greater duration pulses to said third input of said phase comparator in response to an out-of-lock status of said loop, so as to increase the output of said phase comparator to said oscillator.