Peak detection circuit

A peak detection circuit, comprising:

• a differentiating circuit which produces a differentiated signal of an input signal,
• a peak hold circuit which produces a peak value envelope of an output of said differentiating circuit,
• a voltage dividing circuit for dividing an output of said differentiating circuit so as to produce a reference signal,
• a first comparator which receives the output of said differentiating circuit and the reference signal which has a value corresponding to that of an output of said peak hold circuit to compare them with each other, and detects when said input signal falls below said reference signal so as to produce an output representing such a condition,
• a second comparator which detects a portion by which the output of said differentiating circuit exceeds the zero-cross point so as to produce a clock pulse, and
• a flip-flop for producing a signal which rises in accordance with the clock pulse from said second comparator and falls in accordance with the output of said first comparator, the output terminal of said flip-flop being connected to an input terminal of said first comparator via a resistor having a high resistance to attain a hysteresis characteristic in inversion operation of said flip-flop,
• thereby to form an output signal representing a peak of the input signal by the rise of the output of said flip-flop.