Fast exclusive-or and exclusive-nor gates

An EXCLUSIVE-OR (XOR) logic gate comprising:

• an output node;
• a first input node coupled to receive a first logic signal and a second input node coupled to receive a second logic signal, said first and second logic signals being driven between a high and a low voltage potential;
• a first p-channel metal oxide silicon (PMOS) device coupled between said first input node and said output node and having its gate coupled to said second input node, wherein when said second logic signal is at said low voltage potential, said first PMOS device couples said first logic signal to said output node;
• a second PMOS device coupled between said second input node and said output node and having its gate coupled to said first input node, wherein when said first logic signal is at said low voltage potential, said second PMOS device couples said second logic signal to said output node;
• first and second n-channel metal oxide silicon (NMOS) devices coupled in series between said output node and a reference potential substantially equal to said low voltage potential, the gate of said first NMOS device being coupled to said first input node and the gate of said second NMOS device being coupled to said second input node, wherein when said first and second logic signals are both at said high voltage potential said reference potential is coupled to said output node;
• and
• a driving circuit coupled between said output node and said reference potential for driving said output node to said low voltage potential when said first and second logic signals are at said low voltage potential.

An EXCLUSIVE-NOR (XNOR) logic gate having an output node, a first input node coupled to a first logic signal, and a second input node coupled to a second logic signal, said first and second logic signals being driven between a high and a low voltage potential, said XNOR gate comprising:

• a first n-channel metal oxide silicon (NMOS) device being coupled between said first input node and said output node and having its gate coupled to said second input node, wherein when said second logic signal is at said high voltage potential, said first NMOS device couples said first logic signal to said output node;
• a second NMOS device being coupled between said second input node and said output node and having its gate coupled to said first input node, wherein when said first logic signal is at said high voltage potential said second NMOS device couples said second logic signal to said output node;
• first and second p-channel metal oxide silicon (PMOS) devices coupled in series between said output node and a reference potential substantially equal to said high voltage potential, the gate of said first PMOS device being coupled to said first input node and the gate of the second PMOS device being coupled to said second input node, wherein when said first and second logic signals are both at said low voltage potential, said reference potential is coupled to said output node;
• and
• a driving circuit coupled between said output node and said reference potential for driving said output node to said high voltage potential when said first and second logic signals are at said high voltage potential.