ECL latch circuit

An ECL latch circuit comprising a logic section and having a reset function, said logic section including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,

• said first transistor having a collector connected to a ground potential through a first load resistor, and a base serving as a first signal input terminal,
• said second transistor having a collector connected to the ground potential through a second load resistor, a base serving as a second signal input terminal, and an emitter connected to an emitter of said first transistor,
• said third transistor having a collector connected to the collector of said first transistor, and a base for receiving a first reference potential,
• said fourth transistor having a collector connected to the collector of said second transistor, a base for receiving a collector potential of said first transistor through an emitter follower section, and an emitter connected to an emitter of said third transistor,
• said fifth transistor having a collector connected to the collector of said second transistor, a base for receiving a reset signal, and an emitter connected to the emitter of said third transistor,
• said sixth transistor having a collector connected to the emitter of said third transistor, a base serving as a third signal input terminal, and an emitter connected to a low-potential side power supply through a constant current source, and
• said seventh transistor having a collector connected to the emitter of said first transistor, a base serving as a fourth signal input terminal, and an emitter connected to the emitter of said sixth transistor.