High isolation electronic switch

A high isolation electronic MOS gate switch for selectively switching a load between first and second signal input lines, comprising:

• a first MOS gate having a conducting path with a first end connected to the first signal input line, and having a second end;
• a first unity gain buffer having an input connected to the second end of said first MOS gate, and having an output;
• a second MOS gate having a conducting path with a first end connected to the output of said first unity gain buffer and having a second end connected to a common connection point;
• a third MOS gate having a conducting path with a first end connected to the second end of said first MOS gate and the input of said first unity gain buffer and having a second end connected to ground potential;
• a fourth MOS gate having a conducting path with a first end connected to the second signal input line, and having a second end;
• a second unity gain buffer having an input connected to the second end of said fourth MOS gate, and having an output;
• a fifth MOS gate having a conducting path with a first end connected to the output of said second unity gain buffer and having a second end connected to the common connection point;
• a sixth MOS gate having a conducting path with a first end connected to the second end of said fourth MOS gate and the input of said second unity gain buffer and having a second end connected to ground potential;
• a fixed impedance connected between the common connection point and ground potential;
• a third unity gain buffer connected between the common connection point and the load;
• and
• means for supplying a first or second control voltage to a gate port of each of said first, second, third, fourth, fifth and sixth MOS gates, wherein the first control voltage permits conduction by a MOS gate along its conduction path and the second control voltage inhibits conduction by the MOS gate along its conduction path, and wherein the first signal input line is selectively connected to the load when the gate ports of said first, second and sixth MOS gates receive the first control voltage while the gate ports of said third, fourth and fifth MOS gates receive the second control voltage, and wherein the second signal input line is selectively connected to the load when the gate ports of said first, second and sixth MOS gates receive the second control voltage while the gate ports of said third, fourth and fifth MOS gates receive the first control voltage.

An apparatus for electronically switching an output line between a plurality of channels, one of the channels being selectively activated to pass an input signal thereon to the output line while the remaining channels are non-selected, wherein the plurality of channels connect to the output line at a common connection point, comprising:

• a circuit for each of the channels, each said circuit having a first current carrying path for transferring the input signal to the output line when the channel is selectively activated, and a second current carrying path for connecting a portion of the first current carrying path to a ground potential when the channel is non-selected, wherein each said circuit is selectively operated to conduct along only one of its first or second current carrying paths;
• unity gain buffer means for each of the channels connected serially in the first current carrying path of each said circuit for isolating the output line from the input signal when said circuit is selectively conducting along its first current carrying path;
• a fixed impedance connected between the common connection point and ground potential;
• and
• means connected serially in the output line for minimizing effects of a load connected to the output line on said fixed impedance.