Stacked semiconductor memory device and semiconductor memory module containing the same

A semiconductor memory device comprising:

• first and second semiconductor memory chips which are stacked one above the other, each having first and second principal surfaces, each of said first and second semiconductor memory chips having a plurality of first electrodes and a second electrode on said first principal surface;
• first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors;
• and
• a substrate having a main surface and a rear surface, a plurality of first and second wiring patterns formed on said main surface,
• wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, wherein said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, wherein said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, wherein said first electrodes of said first memory chip are electrically connected to each of said first electrodes of said second memory chip via said first and second conductors, and wherein said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip.

A semiconductor memory module comprising:

• first and second semiconductor memory devices, each of said first and second semiconductor memory devices comprising:
• first and second semiconductor memory chips which are stacked one above the other, each of said memory chips having first and second principal surfaces with a plurality of first electrodes and a second electrode being located on the first principal surface;
• first and second connectors, each having a plurality of first conductors arranged on a first surface and a plurality of second conductors arranged on a second surface which is opposite to said first surface, said first conductors being electrically connected to respective ones of said second conductors,
• wherein said first electrodes and said second electrode formed on said first memory chip are electrically connected to respective conductors of said first conductors of said first connector, said first electrodes and said second electrode formed on said second memory chip are electrically connected to respective conductors of said first conductors of said second connector, wherein said first and second connectors are stacked one above the other, said second conductors of said first connector are electrically connected to respective conductors of said first conductors of said second connector, and wherein said first electrodes of said first memory chip are electrically connected to respective electrodes of said first electrodes of said second memory chip via said first and second conductors, said second electrode of said first memory chip is electrically independent of said second electrode of said second memory chip;
• and
• a substrate having a main surface and a rear surface, said semiconductor memory devices being mounted on said main surface of said substrate.