US 5,334,870 AGranted

Complementary MIS transistor and a fabrication process thereof

AssigneeNippondenso Co., Ltd.

InventorsMitsutaka Katada, Hidetoshi Muramoto, Seizi Fuzino, Tadashi Hattori, Katsunori Abe

Life of this patent

Estimating the term…

Loading patent…

Abstract

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Claims9

Dependent claims

A complementary MIS transistor, comprising:

a
substrate;
a P-type well and an N-type well defined in said substrate;
an insulating gate provided on each of said P-type well and said N-type well;
a source region and a drain region both of N-type and formed in said P-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said P-type well;
a source region and a drain region both of P-type and formed in said N-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said N-type well;
and
N-type diffusion regions formed in correspondence to said source region and said drain region in each of said P-type well and said N-type well, said N-type diffusion region having an impurity concentration level that is higher than an impurity concentration level of said P-type well and said N-type well but is lower than an impurity concentration level of said source and drain regions, said N-type diffusion regions extending laterally from said source and drain regions into a part of said substrate located immediately below said first and second edges of said insulating gate, said N-type diffusion regions extending vertically in said substrate to a depth smaller than or equal to a depth of said source and drain regions.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/046,699Filed 16 Apr 1993
Priority: JP 4-12560617 Apr 1992
Granted: 2 Aug 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
Y10S 257/90
Active solid-state devices, e.g. transistors, solid-state diodes: mOSFET type gate sidewall insulating spacer