Thin film transistor (TFT) loads formed in recessed plugs

A process for forming a thin film transistor (TFT) fabricated on a supporting substrate, said process comprising:

• a) forming a planarized insulative layer overlying said supporting substrate;
• b) forming a conductive film overlying said planarized insulative layer;
• c) forming an etch stop layer overlying said conductive film;
• d) patterning said conductive film, said etch stop layer and said planarized insulative layer such that first and second openings expose first and second conductive lines, respectively, said first and second conductive lines comprising a conductive material;
• e) forming a recessed conductive material in said first opening and forming a non-recessed conductive material in said second opening thereby by forming a recessed conductive plug and a non-recessed conductive plug;
• f) forming a patterned gate insulative layer overlying and conforming to said recessed conductive plug, said patterned gate insulative layer having openings to expose said non-recessed conductive plug;
• g) forming a patterned semiconductive film overlying and conforming to said patterned gate insulating layer and said conductive plugs;
• h) introducing first conductive impurities into said semiconductive film at an angle to form a TFT source/drain region in the substantially vertical walls of said semiconductive film at said recessed conductive plug and to form a TFT channel region in the substantially horizontal portion of said semiconductive film that overlies said recessed conductive plug, said recessed conductive plug functioning as a TFT control gate;
• and
• i) introducing second conductive impurities into said semiconductive film that extends from said recessed conductive plug and overlies and connects to said non-recessed conductive plug to form a TFT source/drain connection region.

A thin film transistor (TFT) fabricated on a supporting substrate, said TFT comprising:

• a) a recessed conductive plug serving as a control gate;
• b) a control gate insulating layer;
• c) a film of semiconductive material connecting to and overlapping said recessed plug, said film having vertical regions extending above said recessed plug and horizontal regions extending over said recessed plug;
• wherein, said vertical regions above said recessed plug are conductively doped to form TFT source/drain regions and the horizontal region spanning between said vertical regions above said recessed plug is conductively doped to form a TFT channel region and the horizontal regions outside said recessed plug are conductively doped to form a TFT source/drain interconnect.

A thin film transistor (TFT) fabricated on a supporting substrate, said TFT comprising:

• a) a first recessed conductive plug serving as a control gate;
• b) a control gate insulating layer;
• c) a second recessed conductive plug serving as a source/drain region interconnect;
• d) a film of semiconductive material connecting to and overlapping said first and second recessed plugs, said film having vertical regions extending above said recessed plugs and horizontal regions extending over said recessed plugs;
• wherein, said vertical regions above said first recessed plug are conductively doped to form TFT source/drain regions and the horizontal region spanning between said vertical regions above said first recessed plug is conductively doped to form a TFT channel region, said vertical regions above said second recessed plug are conductively doped to form TFT source/drain resistive regions and the horizontal region spanning between said vertical regions above said second recessed plug is conductively doped to form a TFT source/drain interconnect.

A thin film transistor (TFT) fabricated on a supporting substrate, said TFT comprising:

• a) a recessed conductive plug serving as a control gate;
• b) a control gate insulating layer;
• c) a non-recessed conductive plug serving as a source/drain region interconnect;
• d) a film of semiconductive material connecting to and overlapping said plugs, said film having vertical regions extending above said recessed plug and horizontal regions extending over said recessed and non-recessed plugs;
• wherein, said vertical regions above said recessed plug are conductively doped to form TFT source/drain regions and the horizontal region spanning between said vertical regions above said recessed plug is conductively doped to form a TFT channel region, said horizontal region above said non-recessed plug is conductively doped to form a TFT source/drain interconnect.