Method and configuration for reducing electrical noise in integrated circuit devices
AssigneeTexas Instruments Incorporated
InventorMichael A. Lamson
Life of this patent
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Abstract
A chip packaging configuration prevents differential electrical coupling within a plurality of associated bit lines (14 and 16) by associating, under lead frame (26), a first packaging material having a first dielectric constant and a second packaging material having a second dielectric constant and where the first packaging material and second packaging material are configured to expose the plurality of associated bit lines (14 and 16) to allow approximately equal coupling to lead frame (26) for each bit line (14 and 16) through the first and second dielectric constant to thereby prevent differential electrical coupling of the plurality of bit lines (14 and 16) with lead frame (26).
Claims11
A chip packaging configuration for preventing differential electrical coupling with a plurality of associated bit lines, comprising:
- an integrated circuit chip having a lead frame electrically coupled with said plurality of associated bit lines, said plurality of associated bit lines being near a surface of said integrated circuit chip;
- a first packaging material having a first dielectric constant covering a first portion of said surface and associated between said plurality of associated bit lines and said lead frame;
- a second packaging material having a second dielectric constant covering a second portion of said surface and associated between said plurality of bit lines and said lead frame;
- said first packaging material and said second packaging material associated with said plurality of associated bit lines to expose each of said plurality of bit lines to allow approximately equal coupling to said lead frame for each bit line through said first dielectric constant and said second dielectric constant to thereby prevent differential electrical coupling of said plurality of associated bit lines with said lead frame.
A method for preventing differential electrical coupling of a plurality of associated bits with a chip packaging configuration, comprising the steps of:
- electrically coupling a lead frame with a plurality of associated bit lines of an integrated circuit chip, said plurality of associated bit lines being near a surface of said integrated circuit chip;
- covering a first portion of said surface with a first packaging material having a first dielectric constant and positioning said first packaging material between said plurality of associated bit lines and said lead frame;
- covering a second portion of said surface with a second packaging material having a second dielectric constant and positioning said second packaging material between said plurality of associated bit lines and said lead frame;
- associating said first packaging material and said packaging material with said plurality of associated bit lines to expose each of said plurality of bit lines to allow approximately equal coupling to said lead frame for each bit line through said first dielectric constant and said second dielectric constant to there by prevent differential coupling of said plurality of associated bit lines with said lead frame.
Dependencies are inferred from the claim text.