Method of forming thin silicon mesas having uniform thickness
AssigneeInternational Business Machines Corporation
InventorsGeorge W. Doerre, Seiki Ogura, Nivo Rovedo
Life of this patent
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Abstract
An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.
Claims10
A method of forming isolated silicon mesas from a wafer having a bulk silicon substrate, an insulating oxide layer disposed above said substrate and a silicon device layer above said oxide layer, comprising the steps of:
- forming a set of trenches in said device layer, said trenches being disposed to define a plurality of silicon mesas and extending from a first device layer surface down to said oxide layer, whereby said trenches have a bottom surface of oxide;
- depositing a gauge layer of polycrystalline silicon having a predetermined gauge thickness in said set of trenches;
- oxidizing said gauge layer of polysilicon to form an oxide polish gauge layer of predetermined polish gauge thickness, related to said predetermined gauge thickness, in said trenches, whereby said mesas are surrounded by said oxide polish gauge layer having an oxide gauge surface said predetermined polish gauge thickness above said first layer surface;
- and
- polishing said mesas by chemical-mechanical polishing until said mesas are substantially co-planar with said oxide gauge surface, whereby said oxide polish gauge layer acts as a thickness gauge to establish a mesa thickness of said mesas.
A method of forming an integrated circuit having devices formed in isolated silicon mesas in a device layer from a wafer having a bulk silicon substrate, an insulating oxide layer disposed above said substrate and a silicon device layer above said oxide layer, comprising the steps of:
- forming a set of trenches in said device layer, said trenches being disposed to define a plurality of silicon mesas and extending from a first device layer surface down to said oxide layer, whereby said trenches have a bottom surface of oxide;
- depositing a gauge layer of polycrystalline silicon having a predetermined gauge thickness in said set of trenches;
- oxidizing said gauge layer of polysilicon to form an oxide polish gauge layer of predetermined polish gauge thickness, related to said predetermined gauge thickness, in said trenches, whereby said mesas are surrounded and electrically isolated by said oxide polish gauge layer having an oxide gauge surface said predetermined polish gauge thickness above said first layer surface;
- polishing said mesas by chemical-mechanical polishing until said mesas are substantially co-planar with said oxide gauge surface, whereby said oxide polish gauge layer acts as a thickness gauge to establish a mesa thickness of said mesas;
- forming a plurality of electrical devices in said plurality of silicon mesas;
- forming at least one interlayer dielectric above said oxide polish gauge layer;
- and
- forming a set of device interconnections extending above said polish gauge layer to connect said plurality of electrical devices in an integrated circuit.
Dependencies are inferred from the claim text.