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AssigneeIntel Corporation
InventorMickey L. Fandrich
Estimating the term…
Circuitry for handshaking between a command state machine and write state machine is described. The handshaking circuitry, the command state machine and the write state machine are part of a non-volatile semiconductor memory device that includes a memory array. The command state machine receives commands from a user and communicates valid commands to the write state machine, which responds by performing automated program and erasure operations on the memory array, as appropriate. The command state machine identifies valid commands based upon signals generated by the handshaking circuitry. The handshaking circuitry includes three latches, an OR gate and a NAND gate. The serially coupled latches store an idle signal from the write state machine. The OR gate is coupled to outputs from the second and third of the serially coupled latches and generates a signal indicative of the whether the write state machine is idle. The NAND gate generates another signal indicative of whether the write state machine is busy based upon a start signal, a finished signal and a delayed idle signal. Also described are a method of handshaking between the write state machine and the command state machine and circuitry for powering up and powering down the write state machine.
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the handshaking circuitry comprising:
Circuitry for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the circuitry for controlling the timing of signals between the write state machine and the command state machine comprising:
Circuitry for stopping a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for stopping the write state machine comprising:
Circuitry for powering up and powering down a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for powering up and powering down the write state machine comprising:
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the handshaking circuitry comprising:
A method for handshaking in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for handshaking comprising the sequential steps of:
A method for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine,the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for controlling the timing of signals between the write state machine and the command state machine comprising the sequential steps of:
Dependencies are inferred from the claim text.