Combined queue for invalidates and return data in multiprocessor system

A method of operating a computer system, comprising the steps of:

• making read requests by a CPU to a system memory;
• storing a subset of said system memory in a cache operated by said CPU;
• receiving and buffering return data from said system memory and invalidates for data in said cache, said buffering including:
• separately buffering said return data and said invalidates in first and second buffers of different sizes;
• maintaining in each entry of said first and second buffers an identification of a location in either of said first and second buffers of a next entry in combined order of receipt;
• maintaining a single pointer to the combined next entry of said first and second buffers to be sent to said CPU, said pointer being set in response to said identification and referencing said next entry regardless of whether it is in said first buffer or said second buffer.

A bus interface device for connecting a CPU to a system bus, the CPU including a cache, the bus interface device receiving read data and invalidates from said system bus, comprising:

• a first buffer for receiving said invalidates from said system bus for forwarding to said cache, each invalidate being loaded to said first buffer as an entry;
• a second buffer for receiving said return data from said system bus for forwarding to said cache, each item of return data being loaded to said second buffer as an entry;
• each said entry in said first buffer and said second buffer storing a location of a next combined chronological entry in either said first or second buffers;
• and
• a pointer responsive to said stored location to identify a combined next one of said entries of said first or second buffers to be sent to said CPU regardless of whether said next one is in the first buffer or the second buffer.

An interface device for connecting a processor to a bus, the interface device receiving from said bus first data items having a first data type and receiving from said bus second data items having a second data type, said interface device forwarding said first and second data items to said processor in order of receipt, comprising:

• a first buffer for receiving said first data items of said first data type from said bus, each said first data item of first data type being loaded to said first buffer as an entry;
• a second buffer for receiving said second data items of said second data type from said bus, each said second data item of second data type being loaded to said second buffer as an entry;
• each one of said entries in said first buffer and in said second buffer storing a location of a combined next chronological entry in either said first or second buffers;
• and
• a pointer responsive to said stored location to identify a combined next one of said entries of said first or second buffers to be forwarded to said processor regardless of whether said next one is in the first buffer or the second buffer.