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US 5,333,282 AGranted
Semiconductor integrated circuit device with at least one bipolar transistor arranged to provide a direct connection between a plurality of MOSFETs
AssigneeHitachi, Ltd.
InventorsHideo Maejima, Ikuro Masuda
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit device having at least two logic blocks each including at least two logic units each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten the critical path of a logic block.
Claims65
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a microprogram memory means for storing a microinstruction, wherein said microprogram memory means comprises a plurality of MOSFETs;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal, wherein said microinstruction decoding means comprises a plurality of MOSFETs;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit comprising a plurality of MOSFETs, said arithmetic logic unit being connected to said second internal bus,
- a plurality of operation registers, each comprising a plurality of MOSFETs, said operation registers being connected to said second internal bus,
- an input register comprising a plurality of MOSFETs, said input register being connected to said second internal bus, and
- an output register comprising a plurality of MOSFETs, said output register being connected to said second internal bus and connected to said first internal bus to provide a path for the transfer of data,
- wherein the connection between the output register and the first internal bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the output register and other MOSFET circuits having inputs connected to said first internal bus.
7 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a microprogram memory means for storing a microinstruction, wherein said microprogram memory means comprises a plurality of MOSFETs;
- and
- a microinstruction decoding means comprising a plurality of MOSFETs, for decoding the microinstruction of said microprogram memory means into a control signal, wherein the microinstruction decoding means is connected to a processing circuit to provide a path for the microinstruction control of the processing circuit, and wherein the connection of the microinstruction decoding means and the processing circuit includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the microinstruction decoding means and other MOSFET circuits in said processing circuit,
- wherein said processing circuit responsive to the control signal includes:
- an arithmetic logic unit comprising a plurality of MOSFETs, said arithmetic logic unit being connected to said second internal bus,
- a plurality of operation registers, each comprising a plurality of MOSFETs, said operation registers being connected to said second internal bus,
- an input register comprising a plurality of MOSFETs, said input register being connected to said second internal bus, and
- an output register comprising a plurality of MOSFETs, said output register being connected to said second internal bus and connected to said first internal bus.
6 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means for storing data, and including a plurality of memory cells each having at least one MOSFET, wherein said memory means is connected to said first internal bus to provide a path for the transfer of data;
- a microprogram memory means for storing a microinstruction, wherein said microprogram memory means comprises a plurality of MOSFETs;
- a microinstruction decodng means for decoding the microinstruction of said microprogram memory means into a control signal, wherein said microinstruction decoding means comprises a plurality of MOSFETs;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit comprising a plurality of MOSFETs, said arithmetic logic unit being connected to said second internal bus,
- a plurality of operation registers, each comprising a plurality of MOSFETs, said operation registers being connected to said second internal bus,
- an input register comprising a plurality of MOSFETs, said input register being connected to said second internal bus, and
- an output register comprising a plurality of MOSFETs, said output register being connected to said second internal bus and connected to said first internal bus,
- wherein the connection between the memory means and the first internal bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the MOSFETs of the memory means and other MOSFET circuits having inputs connected to said first internal bus.
8 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a microprogram memory means for storing a microinstruction, wherein said microprogram memory means comprises a plurality of MOSFETs;
- a microinstruction decodng means comprising a plurality of MOSFETs, for decoding the microinstruction of said microprogram memory means into a control signal, and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit comprising a plurality of MOSFETs, said arithmetic logic unit being connected to said second internal bus to provide a path for the transfer of data,
- a plurality of operation registers, each comprising a plurality of MOSFETs, said operation registers being connected to said second internal bus,
- an input register comprising a plurality of MOSFETs, said input register being connected to said second internal bus, and
- an output register comprising a plurality of MOSFETs, said output register being connected to said second internal bus and connected to said first internal bus,
- wherein the connection between the arithmetic logic unit and said second internal bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the arithmetic logic unit and other MOSFET circuits having inputs connected to said second internal bus.
6 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer comprising a first stage comprising a plurality of MOSFETs responsive to an address signal for converting said address signal to a pair of positive and negative signals, and a second stage connected to an address decoder for decoding the pair of positive and negative signals to a word signal, said address decoder comprising a plurality of MOSFETs,
- a word line driver responsive to the word signal for charging a word drive line of said memory cells, said word line driver including a MOSFET for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit for sensing the bit line of said memory cells, and
- an output buffer to be responsive to an output signal of said sense circuit, said output buffer being connected to the first bus,
- a microprogram memory means for storing a microinstruction;
- a microninstruction decodng means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the second stage of the address input buffer comprises at least one bipolar transistor, and wherein the word line driver comprises at least one bipolar transistor arranged to provide a direct connection between the MOSFETs of the word driver and MOSFETs in said memory cells.
14 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer responsive to an address signal for converting said address signal to a pair of positive and negative signals,
- an address decoder for decoding the pair of positive and negative signals to a word signal,
- a word driver responsive to the word signal for charging a word drive line of said memory cells, and for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit comprising a plurality of MOSFETs for sensing the bit line of said memory cells,
- an output buffer comprising a plurality of MOSFETs to be responsive to an output signal of said sense circuit, said output buffer being connected to the first internal bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the precharge circuit and the sense circuit are each comprised of at least one bipolar transistor, and wherein the connection of the output buffer to the first internal bus is through at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the output buffer and other MOSFET circuits having inputs connected to said first internal bus.
15 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer comprising a first stage comprising a plurality of MOSFETs responsive to an address signal for converting said address signal to a pair of positive and negative signals, and a second stage connected to an address decoder for decoding the pair of positive and negative signals to a word signal, said address decoder comprising a plurality of MOSFETs,
- a word driver responsive to the word signal for charging a word drive line of said memory cells, said word driver including a MOSFET for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit for sensing the bit line of said memory cells, and
- an output buffer to be responsive to an output signal of said sense circuit, said output buffer being connected to the first bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the second stage of the address input buffer includes at least one bipolar transistor arranged to provide a direction connection between the plurality of MOSFETs of the first stage of the address input buffer and said plurality of MOSFETs in said address decoder.
14 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer comprising a first stage comprising a plurality of MOSFETs responsive to an address signal for converting said address signal to a pair of positive and negative signals, and a second stage connected to an address decoder for decoding the pair of positive and negative signals to a word signal, said address decoder comprising a plurality of MOSFETs,
- a word line driver responsive to the word signal for charging a word drive line of said memory cells, said word line driver including a MOSFET for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit for sensing the bit line of said memory cells, and
- an output buffer to be responsive to an output signal of said sense circuit, said output buffer being connected to the first bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the word line driver comprises at least one bipolar transistor arranged to provide a direction connection between the MOSFET of the word driver and MOSFETs in said memory cells.
14 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer responsive to an address signal for converting said address signal to a pair of positive and negative signals,
- an address decoder for decoding the pair of positive and negative signals to a word signal,
- a word driver responsive to the word signal for charging a word drive line of said memory cells, and for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit comprising a plurality of MOSFETs for sensing the bit line of said memory cells, and
- an output buffer comprising a plurality of MOSFETs to be responsive to an output signal of said sense circuit, said output buffer being connected to the first internal bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the precharge circuit comprises at least one bipolar transistor arranged to provide a direct connection between a MOSFET of the precharge circuit and MOSFETs of said memory cells.
15 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer responsive to an address signal for converting said address signal to a pair of positive and negative signals,
- an address decoder for decoding the pair of positive and negative signals to a word signal,
- a word driver responsive to the word signal for charging a word drive line of said memory cells, and for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit comprising a plurality of MOSFETs for sensing the bit line of said memory cells, and
- an output buffer comprising a plurality of MOSFETs to be responsive to an output signal of said sense circuit, said output buffer being connected to the first internal bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the sense circuit comprises at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the sense circuit and MOSFETs of said memory cells.
15 more elements
A data processor integrated on a semiconductor substrate comprising:
- first and second internal buses;
- a memory means including:
- a plurality of memory cells each having at least one MOSFET,
- an address input buffer responsive to an address signal for converting said address signal to a pair of positive and negative signals,
- an address decoder for decoding the pair of positive and negative signals to a word signal,
- a word driver responsive to the word signal for charging a word drive line of said memory cells, and for discharging the word drive line of said memory cells,
- a precharge circuit for charging a bit line of said memory cells during a precharge period,
- a sense circuit comprising a plurality of MOSFETs for sensing the bit line of said memory cells, and
- an output buffer comprising a plurality of MOSFETs to be responsive to an output signal of said sense circuit, said output buffer being connected to the first internal bus,
- a microprogram memory means for storing a microinstruction;
- a microinstruction decoding means for decoding the microinstruction of said microprogram memory means into a control signal;
- and
- a processing circuit responsive to the control signal and including:
- an arithmetic logic unit connected to said second internal bus,
- a plurality of operation registers connected to said second internal bus,
- an input register connected to said second internal bus, and
- an output register connected to said second internal bus and connected to said first internal bus,
- wherein the connection of the output buffer to the first internal bus is comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the output buffer and other MOSFET circuits having inputs connected to said first internal bus.
15 more elements
A data processor integrated on a semiconductor substrate comprising:
- a bus;
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and a plurality of MOSFETs controlled by the decoded instructions, and having an output part connected to said bus to provide a path for the transfer of data,
- wherein the connection of the output part of said processing circuit to said bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the processing circuit and other MOSFET circuits having inputs connected to said bus.
2 more elements
A data processor integrated on a semiconductor substrate comprising:
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and a plurality of MOSFETs connected to said instruction decoder,
- wherein the connection of the processing circuit to said instruction decoder provides a path for an instruction control of said data processor, and wherein the connection of the instruction decoder and the processing circuit includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the processing circuit and MOSFET circuits in said instruction decoder.
1 more element
A data processor integrated on a semiconductor substrate comprising:
- a bus;
- a memory having an output part connected to said bus;
- and
- a processor including a logic circuit and a plurality of MOSFETs, and connected to said bus to provide a path for the transfer of data,
- wherein the connection of the output part of the memory and the bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between MOSFETs of the memory and other MOSFET circuits having inputs connected to said bus.
2 more elements
A data processor integrated on a semiconductor substrate comprising:
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and being controlled by the decoded instructions, and comprising a plurality of elements including an arithmetic logic unit, a shifter, an operation register, an input register and an output register, each connected to an internal bus to provide a path for the transfer of data and each comprised of a plurality of MOSFETs,
- wherein the connection of the processing at least one of said elements to said internal bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between MOSFETs of said at least one of said elements and other MOSFET circuits having inputs connected to said internal bus.
1 more element
A data processor comprising:
- a bus;
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and a plurality of MOSFETs controlled by the decoded instructions, and having an output part connected to said bus to provide a path for the transfer of data,
- wherein the connection of the output part of said processing circuit to said bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the processing circuit and other MOSFET circuits having inputs connected t said bus.
2 more elements
A data processor comprising:
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and a plurality of MOSFETs connected to said instruction decoder,
- wherein the connection of the processing circuit to said instruction decoder provides a path for an instruction control of said data processor, and wherein the connection of the instruction decoder and the processing circuit includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between the plurality of MOSFETs of the processing circuit and MOSFET circuits in said instruction decoder.
1 more element
A data processor comprising:
- a bus;
- a memory having an output part connected to said bus;
- and
- a processor including a logic circuit and a plurality of MOSFETs, and connected to said bus to provide a path for the transfer of data,
- wherein the connection of the output part of the memory and the bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between MOSFETs of the memory and other MOSFET circuits having inputs connected to said bus.
2 more elements
A data processor comprising:
- an instruction decoder for decoding instructions;
- and
- a processing circuit including a logic unit and being controlled by the decoded instructions, and comprising a plurality of elements including an arithmetic logic unit, a shifter, an operation register, an input register and an output register, each connected to an internal bus to provide a path for the transfer of data and each comprised of a plurality of MOSFETs,
- wherein the connection of the at least one of said elements to said internal bus includes a buffer comprised of at least one bipolar transistor arranged to provide a direct connection between MOSFETs of said at least of said elements and other MOSFET circuits having inputs connected to said internal bus.
1 more element
A semiconductor device comprising:
- a drive line coupled to a predetermined load;
- a bipolar transistor having a collector-emitter path coupled to said drive line to couple said drive line to a first predetermined potential, wherein a base of said bipolar transistor is coupled to receive a first control signal to control the coupling of said drive line to said first predetermined potential through said collector-emitter path to charge said drive line;
- and
- a field-effect transistor having a source-drain path coupled to said drive line to couple said drive line to a second predetermined potential, wherein a gate of said field-effect transistor is coupled to receive a second control signal to control the coupling of said drive line to said second predetermined potential through said source-drain path to discharge said drive line,
- wherein the bipolar transistor is arranged to provide a direct connection between the field-effect transistor and other field-effect transistor circuits coupled to said bipolar transistor.
2 more elements
A word line drive circuit for a semiconductor memory device comprising:
- a plurality of word drive lines respectively coupled to predetermined word lines of a semiconductor memory;
- a plurality of bipolar transistors respectively coupled to have collector-emitter paths coupled to corresponding word drive lines to couple said word drive lines to a first predetermined potential, wherein bases of said bipolar transistor are respectively coupled to receive first control signals to control the coupling of said word drive lines to said first predetermined potential through said collector-emitter paths to charge said word drive lines;
- and
- a plurality of field-effect transistors having source-drain paths respectively coupled to said word drive lines to couple said word drive lines to a second predetermined potential, wherein gates of said field-effect transistors are respectively coupled to receive second control signals to control the coupling of said word drive lines to said second predetermined potential through said source-drain paths to discharge said word drive lines,
- wherein said bipolar transistors are arranged to provide direct connections between the field-effect transistors and other field-effect transistor circuits to said bipolar transistors.
2 more elements
A semiconductor memory device comprising:
- a memory cell array including a plurality of bit lines respectively coupled to predetermined memory cells in said semiconductor cell array;
- a precharge circuit including a plurality of bipolar transistors respectively coupled to have collector-emitter paths coupled to corresponding bit lines to couple said bit lines to a first predetermined potential, wherein bases of said bipolar transistors are respectively coupled to receive first control signals to control the coupling of said bit lines to said first predetermined potential through said collector-emitter paths to charge said bit lines;
- and
- a discharge circuit including a plurality of field-effect transistors having source-drain paths respectively coupled to said bit lines to couple said bit lines to a second predetermined potential, wherein gates of said field-effect transistors are respectively coupled to receive second control signals to control the coupling of said bit lines to said second predetermined potential through said source-drain paths to discharge said bit lines,
- wherein said bipolar transistors are arranged to provide direct connections between the field-effect transistors and other field-effect transistor circuits to said bipolar transistors.
2 more elements
Dependencies are inferred from the claim text.