Method and apparatus for priority selection of commands
AssigneeIntel Corporation
InventorEdward Solari
Life of this patent
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AssigneeIntel Corporation
InventorEdward Solari
Estimating the term…
A method and apparatus for minimizing processor idle time resulting from the transfer of data between the processor and a resource. An intelligent First In First Out (FIFO) queuing scheme provides a basis for the transfer of data between a host bus and a system bus or between a bus and a resource. The FIFO posts write requests and provides an acknowledgement back to an originating resource on the host bus that the write request has been received. This acknowledgement enables the processor to continue processing. The FIFO further provides for detection of conditions where posted information may be processed out of First In First Out order and conditions where FIFO registers may be read from or data fields overwritten. This capability additionally minimizes idle time by reducing the number of posted items that need to be written to a resource during a read cycle to that resource.
A method of controlling access to a resource in a computer system, comprising the steps of:
A method of accessing a resource in a computer system, said resource including at least one addressable memory location, said method comprising the steps of:
A circuit for controlling access to a resource in a computer system, comprising:
A circuit for processing a plurality of write commands to a resource in a computer system, said resource including at least one addressable memory location, each of said write commands comprising a data element and an address in said resource, said circuit comprising:
Dependencies are inferred from the claim text.