Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers

A graphics computer system comprising:

• a. graphics memory circuits including random access memory, said random access memory for storing bit mapped display data signals representing said visual image and for storing source data, said graphics memory circuits for storing instruction signals used for said processing said source data and said display data;
• b. video display circuits connected to said video random access memory, said video display circuits for forming said visual image in response to receipt of said display data;
• and
• c. graphics processor circuits including central processing unit circuits capable of performing general purpose data processing, including a number of arithmetic and logic operations normally included in a general purpose processing unit, by executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said source data to produce said display data in response to executing said instructions, said central processing unit circuits including a control bus of control signals corresponding to the instruction being executed, and arithmetic and logic unit circuits having plural parts that are each connected to and operate under control of the control bus of control signals and that each perform arithmetic and logic operations in response to the control signals, said central processing unit circuits also including gating circuits selectively controlling propagation between said plural parts.

A graphics system arrangement comprising:

• a. host processing system terminals adapted for connection to a host processing system that determines the content of a visual display to be presented to a user by supplying host data;
• b. graphics memory circuits including random access memory, said random access memory for storing bit mapped display data signals representing said visual image and for storing said host data, said graphics memory circuits for storing instruction signals used for processing said host data and said display data;
• c. graphics processor circuits connected to said host processing system terminals and said graphics memory circuits, said graphics processor circuits operating to transfer host data received at said host terminals to said graphics memory circuits and to process said host data and display data in response to executing said instruction signals stored in said graphics memory circuits, said graphics processor circuits including a control bus of control signals corresponding to the instruction being executed, and arithmetic and logic unit circuits having plural parts that are each connected to and operate under control of the control bus of control signals and that each perform arithmetic and logic operations in response to the control signals, said central processing unit circuits also including gating circuits selectively controlling propagation between said plural parts;
• d. video palette circuits coupled to said graphics memory circuits and operating to convert said bit mapped display data signals from said graphics memory circuits to video level output signals;
• e. video connector terminals adapted for connection to a video display that presents a visual image to a user in response to received video image signals;
• and
• f. converter circuits connected to said video palette signals and said video connector terminals for converting said video level output signals to video image signals at said video connector terminals.

A display system comprising:

• a. a display generating a visual image for presentation to a user in response to receiving display data signals;
• b. memory circuits capable of storing host data and said display data and for storing instruction signals used for processing said host data and said display data, said memory circuits producing said display data signals from said display data;
• c. processor circuits including central processing unit circuits capable of performing general purpose data processing, including a number of arithmetic and logic operations normally included in a general purpose processing unit, by executing said instructions accessed from said graphics memory circuits, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions, said central processing unit circuits including a control bus of control signals corresponding to the instruction being executed, and arithmetic and logic unit circuits having plural parts that are each connected to and operate under control of the control bus of control signals and that each perform arithmetic and logic operations in response to the control signals, said central processing unit circuits also including gating circuits selectively controlling propagation between said plural parts;
• and
• d. a host system determining the content of said visual image by causing said host data to be placed in said memory circuits.

A graphics processor comprising:

• a. host interface circuits adapted to control communication with a host processing system furnishing host data;
• b. memory interface circuits adapted to control communication of data and instructions with a memory storing display data, instructions and said host data;
• and
• c. central processing unit circuits connected between said host interface circuits and said memory interface circuits, said central processing unit circuits being capable of performing general purpose data processing including a number of arithmetic and logic operations normally performed in a general purpose processing unit in response to executing said stored instructions, said central processing unit circuits processing at least said host data to produce said display data in response to executing said instructions, said central processing unit circuits including a control bus of control signals corresponding to the instructions being executed, arithmetic and logic unit circuits having plural parts that are each connected to and operate under control of the control bus of control signals and that each perform arithmetic and logic operations in response to the control signals, said central processing unit circuits also including gating circuits selectively controlling propagation between said plural parts.