Digital signal processor for simultaneously processing left and right signals

A digital signal processor having a data input/output circuit for inputting/outputting a right channel data and a left channel data of an audio signal said data input/output circuit comprising:

• a data conversion circuit for performing a serial-parallel conversion on the inputted data and for performing a parallel-serial conversion on an output data to be outputted, said serial-parallel conversion and said parallel-serial conversion being performed in accordance with a clock signal;
• an R-channel dedicated input latch means and an L-channel dedicated input latch means for latching the inputted R-channel and L-channel data from said data conversion circuit, respectively, said R-channel dedicated input latch means latching the inputted R-channel data in response to a falling edge detection signal of a control signal and said L-channel dedicated input latch means latching the inputted L-channel data from said data conversion circuit in response to a rising edge detection signal of said control signal;
• Means for simultaneously processing the inputted R-channel and L-channel data;
• an R-channel dedicated output latch circuit and an L-channel dedicated output latch circuit for latching the R-channel data and the L-channel data to be outputted, respectively;
• an output data switching circuit for selecting, in accordance with the control signal, the data to be outputted therefrom between the R-channel data and the L-channel data sent respectively from said R-channel and L-channel dedicated output latch circuits, the data selected by said output data switching circuit being loaded into said data conversion circuit in response to said falling and rising edge detection signals of the control signal;
• and
• a timing signal generating means for controlling the timings of data latching at each of said input latch means and of data loading from said output data switching circuit to said data conversion circuit, said timing signal generating means including a falling edge detection circuit for detecting a falling edge of said control signal to produce said falling edge detection signal and a rising edge detection circuit for detecting a rising edge of said control signal to produce said rising edge detection signal.