Digital data generation system including programmable dominance latch

Abstract

A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic "1" is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.

Dependencies are inferred from the claim text.