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US 5,333,128 AGranted
Semiconductor memory device having a circuit for reducing frequency of proceeding refresh in data retention mode
AssigneeSamsung Electronics Co., Ltd.
InventorsSeiseung Yoon, Moongone Kim
Life of this patent
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Abstract
A semiconductor memory device of the type needing refresh includes a circuit for reducing the frequency of refresh cycles in data retention mode. A circuit is provided for preventing deterioration to sensing margin of bit lines that may be decreased by a reduction of the frequency of refresh cycles. The deterioration is prevented by increasing the boosting level of word lines.
Claims4
A semiconductor memory device comprising:
- a memory including a plurality of word lines for accessing data stored in the memory;
- a refresh cycle controller for controlling the frequency of the refresh cycles in data retention mode based upon at least one row address bit and a self-refresh signal, the refresh cycle controller comprising means for separately gating said at least one row address bit and a complement of said at least one row address bit and a complement of said at least one row address bit in response to said self-refresh signal;
- and
- a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal.
1 more element
A semiconductor memory device comprising:
- a memory including a plurality of word lines for accessing data stored in the memory;
- a refresh cycle controller for controlling the frequency of refresh cycles in data retention mode based on at least one row address bit and a self-refresh signal;
- and
- a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal, said word line boosting level generator comprising:
- a fourth inverter receiving said self-refresh signal;
- a fifth inverter receiving said clock-enable signal;
- a sixth inverter having an input terminal connected to an output terminal of said fifth inverter;
- a transmission gate having a control terminal connected between the self-refresh signal and an output terminal of the fourth inverter, and an input terminal connected to an output terminal of the sixth inverter;
- a first field effect transistor having a gate terminal connected to the output terminal of the fourth inverter, a drain terminal connected to a voltage supply Vcc, and a source terminal connected to an output terminal of the transmission gate;
- a second field effect transistor having a drain terminal connected to the voltage supply Vcc and a gate terminal and a source terminal connected to the output terminal of the transmission gate;
- a first metal oxide semiconductor capacitor having one terminal connected to the output terminal of the transmission gate;
- a second metal oxide semiconductor capacitor having one terminal connected to the output terminal of the sixth inverter, and another terminal connected to another terminal of the first MOS capacitor;
- a third field effect transistor having a drain terminal connected to the voltage supply Vcc, a gate terminal connected to a precharge signal line, and a source terminal connected to a node formed by said another terminals respectively of the first and second metal oxide semiconductor capacitors;
- and
- a fourth field effect transistor having a drain terminal connected to the node of the first and second metal oxide semiconductor capacitors, a source terminal connected to a voltage supply Vss, and a gate terminal connected to an output disable signal.
12 more elements
Dependencies are inferred from the claim text.