Memory circuit with dual sense amplifier and amplifier control circuitry
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToshiyuki Hiraki, Masayuki Hata
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToshiyuki Hiraki, Masayuki Hata
Estimating the term…
For performing the coincidence detection between data stored in a memory and comparison data supplied from an external at a high speed, the positive data of a memory 1a is transmitted to a positive sense amplifier 2-1, the negative data is transmitted to a negative sense amplifier, and comparison data 5 and the inverted data thereof are respectively inputted as activating signals of the positive and negative sense amplifiers to an activating circuit. Due to the comparison data, the output of the non-activated sense amplifier always becomes "H". On the other hand, the activated sense amplifier senses and outputs its input potential. The output signals of these sense amplifiers are inputted to a coincidence signal outputting circuit to determine a coincidence signal.
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit for comparing data stored in a memory cell with a sense signal as comparison data, comprising:
A semiconductor integrated circuit for comparing data stored in a memory cell with a sense signal as comparison data comprising:
A semiconductor integrated circuit for comparing data stored in a memory cell with a sense signal as comparison data, comprising:
Dependencies are inferred from the claim text.