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US 5,333,121 AGranted
Dynamic semiconductor memory having local read amplifier driver circuits which are optimized with respect to their drive function
AssigneeSiemens Aktiengesellschaft
InventorHeribert Geib
Life of this patent
Estimating the term…
Abstract
The dynamic semiconductor memory which has at least one block of memory (WLB), in which s block of memory has in each case a plurality of bit line blocks (TB, TB' . . . ) which has for each bit line block a local SAN driver (LTN), and possibly also a local SAP driver (LTP) for driving the read amplifiers (LV) belonging to this bit line block (TB), in order to avoid interfering voltage drops on long driver lines, and which has, to achieve an optimized drive function, multi-stage local SAN drivers (LTN) or SAP drivers (LTP) whose transistors generally have different channel widths.
Claims40
A dynamic semiconductor memory, comprising:
- a memory cell array which has at least one block of memory cells connected to a group of word lines;
- read amplifiers, each having an n-channel part and a p-channel part;
- at least one SAN driver per block of memory cells connected to a group of word lines for driving the n-channel parts of the read amplifiers;
- at least one SAP driver per block of memory cells connected to a group of word lines for driving the p-channel parts of the read amplifiers;
- at least one block of memory cells connected to a group of word lines which is subdivided into a plurality of memory blocks, each memory block connected to a group of bit lines, said memory blocks connected to a group of bit lines in turn having a plurality of bit line pairs;
- said word lines having an electrical contact with superimposed conductor tracks which are of low impedance relative to the word lines via word line pins, the bit line pairs respectively located between two respective word line pins of a word line forming a memory block connected to a group of bit lines;
- a single SAN driver for each memory block connected to a respective group of bit lines, forming a local SAN driver and being driven such that a voltage at its output decreases in a piecemeal manner, with different gradients, to enable a fast and at the same time reliable reading;
- and
- one local SAN driver driving the n-channel parts of all read amplifiers belonging to a memory block via a local SAN line.
6 more elements
A dynamic semiconductor memory, comprising:
- a memory cell array which has at least one block of memory cells connected to a group of word lines;
- read amplifiers, each having an n-channel part and a p-channel part;
- at least one SAN driver per block of memory cells connected to a group of word lines for driving the n-channel parts of the read amplifiers;
- at least one SAP driver per block of memory cells connected to a group of word lines for driving the p-channel parts of the read amplifiers;
- at least one block of memory cells connected to a group of word lines which is subdivided into a plurality of memory blocks, each memory block connected to a group of bit lines, said memory blocks connected to a group of bit lines in turn having a plurality of bit lines pairs;
- said word lines being only in a plane of low-impedance material with additional word line drivers, the bit line pairs respectively located between two respective word line drivers of a word line forming a memory block connected to a group of bit lines;
- a single SAN driver for each memory block, forming a local SAN driver and being driven such that a voltage at its output decreases in a piecemeal manner, with different gradients, to enable a fast and at the same time reliable reading;
- and
- one local SAN driver driving the n-channel parts of all read amplifiers belonging to a memory block via a local SAN line.
6 more elements
A dynamic semiconductor memory, comprising:
- a memory cell array which has at least one block of memory cells connected to a group of word lines;
- read amplifiers, each having an n-channel part and a p-channel part;
- at least one SAN driver per block of memory cells connected to a group of word lines for driving the n-channel parts of the read amplifiers;
- at least one SAP driver per block of memory cells connected to a group of word lines for driving the p-channel parts of the read amplifiers;
- at least one block of memory cells connected to a group of word lines which is subdivided into a plurality of memory blocks, each memory block connected to a group of bit lines, said memory blocks connected to a group of bit lines in turn having a plurality of bit lines pairs;
- said word lines being only in a plane of low-impedance material with additional word line drivers, the bit line pairs respectively located between two respective word line drivers of a word line forming a memory block connected to a group of bit lines;
- a single SAN driver for each memory block, forming a local SAN driver and being driven such that a voltage at its output decreases in a piecemeal manner with different gradients, to enable a fast and at the same time reliable reading;
- one local SAN driver driving the n-channel parts of all read amplifiers belonging to a memory block via a local SAN line;
- and
- each of the local SAN drivers having a diode, which is connected to a reference potential on a cathode side thereof and is connected to a first terminal of a first n-channel transistor on an anode side thereof, a second terminal of the first n-channel transistor connected to a driver output of the associated local SAN driver and a gate terminal of the first n-channel transistor driven by a first control signal, a second n-channel transistor connected in parallel with the diode and having a gate terminal that is driven by a second control signal, a first terminal of a third n-channel transistor connected to the driver output of the associated local SAN driver, and a second terminal of the third n-channel transistor connected to the reference potential, and a gate terminal of the third n-channel transistor driven by a third control signal.
7 more elements
A dynamic semiconductor memory, comprising:
- a memory cell array which has at least one block of memory cells connected to a group of word lines;
- read amplifiers, each having an n-channel part and a p-channel part;
- at least one SAN driver per block of memory cells connected to a group of word lines for driving the n-channel parts of the read amplifiers;
- at least one SAP driver per block of memory cells connected to a group of word lines for driving the p-channel parts of the read amplifiers;
- at least one block of memory cells connected to a group of word lines which is subdivided into a plurality of memory blocks, each memory block connected to a group of bit lines, said memory blocks connected to a group of bit lines in turn having a plurality of bit lines pairs;
- said word lines having an electrical contact with superimposed conductor tracts which are of low impedance relative to the word lines via word line pins, the bit line pairs respectively located between two respective word line pins of a word line forming a memory block;
- a single SAN driver for each memory block connected to a respective group of bit lines, forming a local SAN driver and being driven such that a voltage at its output decreases in a piecemeal manner, with different gradients, to enable a fast and at the same time reliable reading;
- one local SAN driver driving the n-channel parts of all read amplifiers belonging to a memory block via a local SAN line;
- and
- each of the local SAN drivers having a diode, which is connected to a reference potential on a cathode side thereof and is connected to a first terminal of a first n-channel transistor on an anode side thereof, a second terminal of the first n-channel transistor connected to a driver output of the associated local SAN driver and a gate terminal of the first n-channel transistor driven by a first control signal, a second n-channel transistor connected in parallel with the diode and having a gate terminal driven by a second control signal, a first terminal of a third n-channel transistor connected to the driver output of the associated local SAN driver, and a second terminal of the third n-channel transistor connected to the reference potential, and a gate terminal of the third n-channel transistor driven by a third control signal.
7 more elements
Dependencies are inferred from the claim text.