US 5,333,120 A · Binary two's complement arithmetic circuit

Abstract

A negation circuit (28) generates a two's complement negation by inverting only those bits of an incoming number which have a level of significance greater than the significance level at which a transition bit resides. The transition bit and all bits of the incoming number having a significance level less than the transition bit are reproduced at the output (32) of the negation circuit (28). The transition bit is the least significant bit in the incoming number to exhibit a logic one. A negation selector circuit (40) selectively overrides the negation so that a negation is generated only when a select negation signal (34) is active. When a transition detected input signal (38) is active, all bits of the incoming number are inverted- A transition detected output signal (36) provides a signal which activates to indicate that the circuit (28) has detected a transition bit. The negation circuit (28) may be coupled to an adder (66) to form a direct subtractor or a direct adder/subtractor (64).

Claims26

Dependent claims

A binary two's complement arithmetic circuit for performing arithmetic operations on an incoming number expressed as N bits, where N is an integer number, where each of said N bits exhibits either a logic zero or a logic one, and where a transition bit of said N bits is the least significant one of said N bits to exhibit a logic one, said circuit comprising:

input means having N terminals adapted to receive said N bits of said incoming number in a one-to-one correspondence;
a combinatorial logic circuit coupled to said input means, said combinatorial logic circuit being configured to invert all bits of said incoming number having greater significance than said transition bit and to transfer, without inverting, said transition bit and all bits having less significance than said transition bit;
and
output means, coupled to said combinatorial logic circuit, having N-1 terminals corresponding to the N-1 most significant ones of said N bits of said incoming number.

1 more element

A binary two's complement arithmetic circuit for directly adding first incoming numbers to second incoming numbers and for subtracting said first incoming numbers from said second incoming numbers, wherein said first incoming numbers are expressed as N bits, where N is an integer number, where each of said N bits exhibits either a logic zero or a logic one, and where a transition one of said N bits is the least significant one of said N bits to exhibit a logic one, said circuit comprising:

input means having N terminals adapted to receive said N bits of said first incoming numbers in a one-to-one correspondence;
a selection terminal adapted to receive a select-negation input signal;
a combinatorial logic circuit coupled to said input means and to said selection terminal, said combinatorial logic circuit having N outputs corresponding to said N bits of said first incoming numbers and being configured to:
invert all bits of said first incoming numbers having greater significance than said transition bits thereof when said select-negation signal is active,
transfer without inverting said transition bits thereof and all bits of said first incoming numbers having less significance than said transition bits when said select-negation signal is active, and
transfer, without inverting, all of said bits of said first incoming numbers when said select-negation signal is inactive;
a binary adder having a first input coupled to said N outputs of said combinatorial logic circuit and having a second input adapted to receive said second incoming numbers.

4 more elements

A binary two's complement arithmetic circuit for performing arithmetic operations on an incoming number expressed as N bits, where N is an integer number, where each of said N bits exhibits either a logic zero or a logic one, and where a transition bit of said N bits i the least significant one of said N bits to exhibit a logic one said circuit comprising:

input means having N terminals adapted to receive said N bits of said incoming number in a one-to-one correspondence,
a first combinatorial logic circuit coupled to said input means, said combinatorial logic circuit detecting the occurrence of the transition bit and inverting all bits of said incoming number having greater significance than said transition bit and transferring, without inverting, said transition bit and all bits having less significance than said transition bit,
output means coupled to said first combinatorial logic circuit having N terminals corresponding to the N bits of said incoming number,
a transition-detected output terminal adapted to provide a transition-detected output signal which is active when the transition bit has occurred and is otherwise inactive,
a select-negation terminal adapted to receive a select-negation input signal, and
the transition-detected output signal being in phase with the select-negation input signal.

3 more elements

Dependencies are inferred from the claim text.

Binary two's complement arithmetic circuit

Life of this patent

Binary two's complement arithmetic circuit

Life of this patent

Abstract

Claims26