Transient reduction circuit

Abstract

A transient reduction circuit is provided for use in an arrangement including a backplane having at least two conductors, a power supply connected to the conductors, and a plurality of circuit cards attached to the backplane and connected to the conductors. Each of the plurality of circuit cards includes a transient reduction circuit having inputs for connection to the power supply output and a reference potential, a transistor having an emitter connected to the power input, a collector connected to the load and a base, a resistor connected between the base and the reference potential input, and a decoupling capacitor connected between the collector and the reference potential input. When the cards are powered the transistor is turned on and saturates, thus introducing only a 0.1 V drop in the power supply line. A sudden decrease in power supply voltage output is prevented from discharging the decoupling capacitor by a reverse biased base-collector junction in the transistor.

Dependencies are inferred from the claim text.