Protection apparatus for series pass MOSFETS
AssigneeSiemens Aktiengesellschaft
InventorsWolfgang H. Krautschneider, Mike A. Killian
Life of this patent
Estimating the term…
Abstract
In order to restrict the voltage across the gate oxide of an input pass-through transistor which operates as an input signal source to a MOS inverter, a MOS transistor wired as a MOS diode is connected between the source and gate electrode of the pass-through transistor. The diode connected transistor allows the use of a thin oxide device for the pass-through transistor which enables a high transconductance device to be employed while restricting the voltage across the gate oxide of the pass-through transistor to an acceptable value.
Claims15
A protection apparatus for protecting the input of a series pass-through FET transistor from excessive voltages applied to the input source or drain terminal electrode of the FET where the source to drain path of said FET transistor is connected between an input terminal and output terminal, comprising:
- a protection FET transistor connected as a FET diode and with said diode connected between said input drain or source terminal and said gate electrode of said pass-through transistor.
A protection apparatus for protecting the input of a series pass-through FET transistor from excessive voltages applied to the input source or drain terminal electrode of the FET where the source to drain path of said FET transistor is connected between an input terminal and output terminal, comprising:
- a protection FET transistor connected as a FET diode and with said diode connected between said input drain or source terminal and said gate electrode of said pass-through transistor;
- and
- an inverter including a P and an N channel FET each having a source, drain and gate electrode, with the source electrode of said P channel FET coupled to a source of operating potential, with the drain electrodes of said P and N channel FETs coupled together to an output, with the source electrode of said N channel FET coupled to a point of reference potential, and with the gate electrodes of said N and P channel FETs connected together and coupled to said drain electrode of said pass-through FET.
A protection circuit for a MOS pass-through FET, comprising:
- a CMOS inverter having a P channel and an N channel MOSFET, each having a drain, source and gate electrode, with the source electrode of said P channel FET adapted to be connected to a source of operating potential, with the drain electrodes of said P and N channel FETs connected together to provide an output terminal with the source electrode of said N channel FET connected to a point of reference potential, and with the gate electrodes of said N and P channel FETs connected together to form an input terminal,
- a series pass-through MOSFET having a source drain and gate electrode and having the source electrode connected to an input terminal pad for receiving input signals, and having the drain electrode connected to the input terminal of said inverter, and having a gate electrode coupled to said source of operating potential, and
- a protection MOSFET transistor having a source, drain and gate electrode and connected as a diode with the common source gate electrode connection of said protection MOSFET connected to the source electrode of said series MOSFET and with the drain electrode of said protection MOSFET connected to the gate electrode of said series MOSFET, whereby when a voltage at said input terminal pad exceeds said operating potential voltage, said protection MOS conducts to limit the voltage (VGS) applied to the gate oxide of said pass-through MOSFET.
Dependencies are inferred from the claim text.