Switched capacitor D/A converter

A digital-to-analog converter (DAC) comprising:

• an input terminal and an output terminal;
• a first power terminal for the application thereto of a first fixed reference potential;
• N weighted storage capacitors;
• each capacitor having first and second plates, with the first plate of each one of said N capacitors being connected in common to said output terminal;
• where N is an integer greater than one;
• N switching transistors, one switching transistor per capacitor, each switching transistor having source and drain electrodes defining the ends of a conduction path and a gate electrode with which there is associated gate capacitance;
• means connecting the conduction path of each switching transistor between the second plate of its corresponding capacitor and said first power terminal;
• means coupled between said input terminal and the gate electrodes of said switching transistors for:
• (a) selectively sampling N digital data signals at said input terminal and coupling each sampled signal to the gate electrode of a different one of each one of said N switching transistors whereby their gate electrodes are charged to a first turn-on level or are discharged to a second turn-off level;
• and (b) selectively precharging the gate capacitance of each one of said N switching transistors to a first turn-on level;
• including means for selectively applying a potential to the gate electrode of all of said N control transistors for turning them all on whereby said N storage capacitors are connected in parallel and charge selectively stored on said storage capacitors is redistributed among all of the storage capacitors for producing an output voltage which represents said digital data signals;
• and
• means for applying a charging potential to said output terminal for charging said output terminal to a second operating potential, whereby those capacitors whose associated switching transistors are charged to said first turn-on level are charged to a value of potential equal to the difference between said second operating potential and said first fixed reference potential.

A digital-to-analog converter (DAC) for converting a set of N data bits to an analog voltage comprising:

• N capacitors and N switching transistors, one capacitor and an associated switching transistor for each one of said N data bits;
• each capacitor having first and second plates;
• means connecting the first plate of each capacitor to an output node;
• each one of said N switching transistors having first and second electrodes defining the ends of a conduction path and a control electrode, each control electrode having associated therewith a relatively small capacitance;
• means connecting the conduction path of each switching transistor between the second plate of its associated capacitor and a first power terminal;
• an input node adapted to receive serially supplied digital data signals during a data load interval and a precharge signal during a precharge interval;
• N selectively enabled data transfer paths, one data transfer path per each one of said N switching transistors, each data transfer path connected between said input node and the control electrode of its associated switching transistor;
• means for selectively turning-on said N data transfer paths, one at time, during said data load interval for selectively sampling the digital data signals and for applying and storing a voltage corresponding to each one of said digital data signals on the gate of a corresponding one of said N switching transistors;
• and
• means for selectively applying a voltage across said capacitors for charging them in accordance with the data responsive voltage levels present on the gate of their respective switching transistors.

A digital-to-analog converter (DAC) for converting N-bit digital values to respective analog voltages comprising:

• an output node with an output capacitor coupled thereto;
• an intermediate node;
• a plurality of capacitors;
• a plurality of switches, one switch associated with each of said plurality of capacitors and forming respective series connections of a capacitor and a switch between said intermediate node and a source of reference potential;
• means for applying said N-bit digital values for controlling said plurality of switches;
• means for charging said intermediate node to at least one predetermined potential during at least one portion of respective sample conversion intervals;
• and
• a further switch, for coupling said intermediate node to said output node during a second portion of respective sample conversion intervals.