Composite logic circuit

A composite logic circuit comprising:

• a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,
• a second input node to which a second logic signal having a logic level changing between said first potential and a third potentials, is supplied,
• a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,
• a first output node for providing a first output signal representing an NAND of said first and second logic signals,
• a second output node for providing a second output signal representing an NAND of said first and third logic signals,
• a first power supply node for receiving a potential equal to said first potential,
• a second power supply potential for receiving a potential equal to said second potential,
• first switching means having one end connected to said first power supply node, and opened and closed in response to said first logic signal,
• second switching means connected between the other end of said first switching means and said first output node, and opened and closed in response to said second logic signal,
• third switching means connected between the other end of said first switching means and said second output node, and opened and closed in response to said third logic signal,
• fourth switching means connected between said second power supply node and said first output node, and opened and closed in response to said second output signal,
• fifth switching means connected between said second power supply node and said second output node, and opened and closed in response to said first output signal,
• sixth switching means connected between said second power supply node and said first output node, and opened and closed in response to said first logic signal, and
• seventh switching means connected between said second power supply node and said second output node, and opened and closed in response to said first logic signal.

A composite logic circuit comprising:

• a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,
• a second input node to which a second logic signal having a logic level changing between said first potential and a third potential is supplied,
• a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,
• a first output node for providing a first output signal representing an NOR of said first and second logic signals,
• a second output node for providing a second output signal representing an NOR of said first and third logic signals,
• first logic means for bringing the respective signal levels of said first and second output signals to said first potential when the potential of said first logic signal is said second potential,
• second logic means for bringing the signal level of said first output signal to said second potential and the signal level of said second output signal to said first potential, when the potential of said first logic signal is said first potential, the potential of said second logic signal is said first potential, and the potential of said third logic signal is said third potential, and
• third logic means for bringing the signal level of said first output signal to said first potential and the signal level of said second output signal to said second potential, when the potential of said first logic signal is said first potential, the potential of said second logic signal is said third potential, and the potential of said third logic signal is said first potential.

A composite logic circuit comprising:

• a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,
• a second input node to which a second logic signal having a logic level changing between said first potential and a third potential is supplied,
• a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,
• a first output node for providing a first output signal representing an NAND of said first and second logic signals,
• a second output node for providing a second output signal representing an NAND of said first and third logic signals,
• first logic means for bringing the respective signal levels of said first and second output signals to said second potential when the potential of said first logic signal is said first potential,
• second logic means for bringing the signal level of said first output signal to said second potential and the signal level of said second output signal to said first potential, when the potential of said first logic signal is said second potential, the potential of said second logic signal is said first potential, and the potential of said third logic signal is said third potential, and
• third logic means for bridging the signal level of said first output signal to said first potential, and the signal level of said second output signal to said second potential, when the potential of said first logic signal is said second potential, the potential of said second logic signal is said third potential, and the potential of said third logic signal is said first potential.