Bipolar-MOS circuits with dimensions scaled to enhance performance

A logic circuit comprising:

• a pull-up section including
• bipolar pull-up means connected between a first terminal and an output of the circuit;
• MOS pull-up means, characterized by a first dimension, driving the bipolar pull-up means and responding to an input signal to force the bipolar pull-up means to provide a low resistance current path for establishing a first logic level at the output if the input signal assumes a second logic level;
• and
• a pull-down section including
• MOS pull-down means, characterized by a second dimension, connected between the output of the circuit and a second terminal, the MOS pull-down means responding to the input signal to provide a low resistance current path for establishing the second logic level at the output if the input signal assumes the first logic level,
• such that
• the first and the second dimension are elated by an optimum ratio that substantially minimizes a propagation delay of the circuit;
• the sum of the first and the second dimension is proportional to an input capacitance of the circuit;
• and
• the optimum ratio is independent of a fanout which is defined as a load capacitance of the circuit divided by the input capacitance, the load capacitance being connected to the output of the circuit.