Transmission gate
AssigneeRohm Co., Ltd.
InventorJun Hirai
Life of this patent
Estimating the term…
Abstract
A transmission gate having a CMOS structure wherein an NMOS transistor and a PMOS transistor are connected in parallel between an input signal line and an output signal line and a separation layer which separates a transistor formation region for one of the PMOS transistor and the NMOS transistor formed in a substrate from the substrate, wherein the back gates of the respective transistors are constituted to receive an input signal from the input signal line when the one transistor and the other transistor formed in a well region are in a conductive state.
Claims19
A transmission gate comprising,
- a CMOS circuit which is formed by connecting in parallel an N channel MOS transistor and a P channel MOS transistor between an input signal line and an output signal line;
- and
- a separation layer which separates a transistor formation region for one of the P channel MOS transistor and the N channel MOS transistor formed in a substrate from the substrate,
- wherein the respective back gates of the transistors are constituted to receive an input signal from the input signal line, when the transistor and the other transistor of the P channel MOS transistor and the N channel MOS transistor are rendered conductive.
A transmission gate comprising,
- channel MOS transistor of which source is connected to an output signal line, of which drain is connected to an input signal line, of which back gate is connected to the input signal line via a first switching circuit and is further connected to a first power source line via a second switching circuit and of which gate is constituted to receive one of a control signal and its inverted signal;
- and
- an N channel MOS transistor of which drain is connected to the output signal line, of which source is connected to the input signal line, of which back gate is connected to the input signal line via a third switching circuit and is further connected to a second power source line having a lower potential than that of the first power source, via a fourth switching circuit and of which gate is constituted to receive the other of the control signal and its inverted signal, and
- wherein said P channel MOS transistor is formed in an N type well region formed in a P type substrate, and said N channel MOS transistor is formed in the substrate and includes an N type buried layer which separates the transistor formation region from the substrate.
An integrated analog signal transmission gate, comprising:
- a substrate;
- an input signal line;
- an output signal line;
- a CMOS circuit having an N channel MOS transistor and a P channel MOS transistor formed in the substrate and conductively in parallel between the input signal line and the output signal line;
- a separation layer conductively separating back gates of the P channel MOS transistor and the N channel MOS transistor from each other;
- and
- switches connecting respective back gates of the transistors to receive respectively an input signal and an inversion of the input signal from the input signal line when the P channel MOS transistor and the N channel MOS transistor are conductive.
An analog signal transmission gate, comprising:
- a substrate;
- an input signal line;
- an output signal line;
- a CMOS circuit having an N channel MOS transistor and a P channel MOS transistor formed in the substrate and conductively in paralel between the input signal line and the output signal line;
- a separation layer conductively separating back gates of the P channel MOS transistor and the N channel MOS transistor from each other;
- and
- switching circuits connecting respective back gates of the transistors to receive respectively different polarity power source voltages only when the P channel MOS transistor and the N channel MOS transistor are not conductive.
Dependencies are inferred from the claim text.