EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells

An EEPROM memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising:

• an array of M.times.N EEPROM cells organized into M horizontally directed rows and N vertically directed columns;
• a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell;
• said source region comprising a lightly doped region and a heavily doped region;
• said lightly doped region positioned closer to said drain;
• said drain region comprising a heavily doped region;
• a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate and directly over said bit line regions, separated therefrom by a layer of a first insulator, and oriented in a substantially horizontal direction, said sets forming plurality of pairs of first control lines, with each of said pairs including one first control line from said first set and one adjacent first control line from said second set, with each of said first control lines in said pairs being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell between said source region and said drain region being a channel region of said given cell;
• a set of M.times.N floating gates, with each floating gate included in a given one of ht cells in said array, with each floating gate including a first section disposed below said first control line associated with a given cell and disposed over said channel region, and with each floating gate including a second section spaced apart from said channel region of said given cell;
• and
• a set of second control lines, spaced apart from said channel regions in associated said given cells, each of said second control lines insulatively disposed directly over said conductive bit line regions in an area of said substrate associated with memory cells of rows that are associated with one of said pairs of said first control lines and disposed over said second sections of said floating gates associated with said pair of associated first control lines.

An architecture for a programmable non-volatile memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising:

• an array of M.times.N programmable non-volatile cells organized into M rows and N columns;
• a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a thin insulator, and oriented in a substantially horizontal direction, with each of said first control lines being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell being a channel region of said given cell, with said channel region disposed between said drain region and said source region of said given cell;
• a set of bit line diffusions of a second conductivity type integrally formed along the major surface of said substrate, each constituting a conductor that is continuous with and joining at least three of said rows, said bit line diffusions forming plurality of adjacent pairs of bit line diffusions, each pair with:
• i) a first bit line diffusion in a given pair of adjacent bit line diffusions forming a drain region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a source region for said given cell associated with said second set of said first control lines,
• ii) said first bit line diffusion in a given pair of adjacent bit line diffusions forming a source region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a drain region for said given cell associated with said second set of said first control lines;
• and
• a set of M.times.N polysilicon floating gates, with each floating gate included in a given one of the cells in said array, with each floating gate disposed below the word line conductor associated with said given cell and disposed over at least a portion of said channel area.

A programmable non-volatile memory, formed on a semiconductor substrate having a major surface, said memory comprising:

• an array of M.times.N electrically writable and electrically readable non-volatile memory cells organized into M rows oriented along a first axis and N rows oriented along a second axis that is orthogonal to said first axis;
• a first set of charge emitting control means and a second set of charge emitting control means oriented along said first axis, said sets forming plurality of pairs of charge emitting control means, with each of said pairs including one charge emitting control means from said first set and one adjacent charge emitting control means from said second set, with each of said charge emitting control means in said pairs being associated with plurality of memory cells only within a given one of said M rows in said array;
• a set of second control lines organized so that each of said second control lines insulatively disposed along said substrate, only associated with a corresponding one of said pairs of charge emitting control means, and associated with at least one of said memory cells in each of said M rows that are associated with said corresponding pair of first charge emitting control means;
• and
• each of said charge emitting means is the only conductor means that is connected to plurality of memory cells within said given one of said M rows of said array and is not connected to adjacent one of said M rows.

In an EEPROM array, having a plurality of bit lines oriented parallel to a vertical axis and plurality of word lines oriented parallel to a horizontal axis, with said array including N.times.M EEPROM cells formed along a major surface of a semiconductor substrate of a first conductivity type, an architecture for said array comprising:

• four floating gates, with each of said floating gates included in a corresponding EEPROM cell and with each floating gate comprised of an elongated member that has a short side and a long side, said floating gate member having a programming section and an erase section disposed along an individual axis, wherein said individual axis of each of said floating gates member passes along said long side of a corresponding floating gate, and said corresponding individual axis is not parallel to said horizontal axis of said word lines and is not perpendicular to the surface of said substrate;
• said programming section of each of said floating gates being disposed over at lest a portion of a corresponding channel region of a field effect transistor that is formed in said substrate and all said programming section is separated from said channel region by only an insulator that has a dielectric constant;
• an erase conductor structure having erase regions coupled by connecting regions, with said four floating gates oriented so that the erase sections of said floating gates are insulatively disposed under said erase regions;
• and
• said four corresponding EEPROM cells connect to a first bit line region of a second conductivity type that is integrally formed within said substrate;
• whereby at least a portion of said first bit line region of said second conductivity type is insulatively disposed directly under at least a portion of said erase conductor structure.

A programmable non-volatile memory transistor formed along a semiconductor substrate of a first conductivity type comprising:

• a floating gate structure disposed over a first region of said substrate, said floating gate structure including a first dielectric layer having a first thickness disposed over said substrate, a first conductive gate member having a chemically engraved surface disposed over said first dielectric layer and said floating gate structure also including a second dielectric layer disposed over and conformal with at least a portion of said engraved surface of said first conductive gate member;
• first impurities of a second conductivity type integrally formed along two spaced-apart second regions of said substrate, each of said second region extending from said first region;
• and
• a second conductive control gate member disposed over and conformal with said second dielectric layer, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said second conductive control gate member in all modes of operations of said memory transistor, and said structure also increases the capacitance between said first and second conductive gate members and thereby reduces the operating voltage of said memory cell under the operating voltage condition of said memory cell.

A non-volatile programmable semiconductor memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising:

• an array of M.times.N memory cells organized into M horizontally directed rows and N vertically directed columns;
• a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell;
• a set of M.times.N floating gate structures, with each floating gate structure included in a given one of the cells in said array, with each floating gate structure comprising a thin gate oxide disposed over a channel region of a field effect transistor, said channel disposed between said source region and said drain region of said given cell, a first conductive gate member disposed over said gate oxide and having a chemically engraved surface, and said structure also comprising a second dielectric layer disposed over and conformal with said engraved surface;
• and
• a set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a first thin insulator, and oriented in a substantially horizontal direction, with at least one of said first control lines being associated with each of said rows, said associated first control line being disposed over and conformal with a corresponding said second dielectric layer to form a first capacitor with said associated first gate member within each memory cell, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said first control line in all modes of operation of said memory cell and under the operating voltage condition of said memory cell.