Circuit arrangement for bit rate adjustment to two digital signals
AssigneeU.S. Philips Corporation
InventorRalph Urbansky
Life of this patent
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Abstract
A buffer memory, in which a first signal is written and from which a second signal is read out, and a subtractor which forms the difference between the counts of a read counter and a write counter, which control reading and writing. A justification decision circuit generates a stop signal for the read counter. An accumulator accumulates the difference signal over a predetermined time interval. The accumulator output, delayed by a time interval and weighted with a second factor, and a justification signal denoting the number of stuff bits caused by the justification decision circuit between two stop instants, are added to the subtractor output in the accumulator.
Claims24
A circuit arrangement for bit rate adjustment, comprising:
- a buffer memory,
- a write counter for controlling writing of a first digital signal into said memory at a first bit rate,
- a read counter for controlling reading of a second digital signal from said memory at a second bit rate higher than said first bit rate,
- means for receiving the second digital signal read from said memory,
- a subtractor for forming a difference signal by determining the difference between the counts of said read and said write counters, and
- a justification decision circuit for generating stop signals for said read counter,
- characterized in that the arrangement includes means for inserting into said second digital signal, in said means for receiving, a number of stuff bits between two of the stop signals,
- the justification decision circuit comprises an accumulator having an output signal;
- time delay means for weighting by a first factor, and delaying by a first given time interval, at least a portion of said output signal to produce a secondary signal;
- and means, responsive to said accumulator output signal, for generating one of said stop signals for the read counter and providing a justification signal representing said number of stuff bits, and
- said accumulator comprises means for accumulating, over a second given time interval, said difference signal, said secondary signal and said justification signal.
A circuit arrangement for bit rate adjustment, comprising:
- a buffer memory,
- a write counter for controlling writing of a first digital signal into said memory at a first bit rate,
- a read counter for controlling reading of a second digital signal from said memory at a second bit rate higher than said first bit rate,
- a subtractor for forming a difference signal by determining the difference between the counts of said read and said write counters, and
- a justification decision circuit for generating stop signals for said read counter,
- characterized in that the arrangement includes a selection matrix for receiving the second digital signal read from said memory, and for inserting stuff bits into said second digital signal, and
- the justification decision circuit comprises an accumulator having an output signal;
- time delay means for weighting by a first factor, and delaying by a first given time interval, at least a portion of said output signal to produce a secondary signal;
- and means, responsive to said accumulator output signal, for generating one of said stop signals for the read counter and providing a justification signal representing said number of stuff bits,
- said accumulator comprises means for accumulating, over a second given time interval, said difference signal, said secondary signal and said justification signal, and
- said means for generating comprises a track counter circuit for
- a) determining the justification signal for the number of bits to be stuffed in the selection matrix,
- b) counting the stuffed bits, modulo-n, and
- c) generating a stop signal for the read counter for
- the duration of an accumulation time interval after
- counting n stuffed bits.
Dependencies are inferred from the claim text.