Device for processing the Viterbi algorithm comprising a processor and a dedicated operator

A device for recovering an original bit stream b(i) from a received bit stream by processing said received bit stream in accordance with a Viterbi algorithm, said device comprising a processor, said Viterbi algorithm being defined by a constraint length of value n+1 and 2.sup.n states associated with streams of bits, characterized in that said device comprises an operator (C, COMP, MUX, S1, S3) coupled to said processor for processing said Viterbi algorithm with said processor for establishing a maximal metric of rank r of a state E.sub.j denoted Met.sub.r (E.sub.j), for r greater than n, where r and n are integers, and the (r-n)th bit of the received bit stream corresponding to said maximal metric from input values which are maximal metrics of rank r-1 of states E.sub.2k and E.sub.2k+1 denoted Met.sub.r-1 (E.sub.2k) and Met.sub.r-1 (E.sub.2k+1) and the conditional probabilities related to said states E.sub.2k and E.sub.2k+1 that the r-th bit of bit streams associated with these states has a determined valued denoted Pr(b(r)=O/E.sub. 2k) and Pr(b(r)=O/E.sub.2k+1), where k is equal to 2j for any value of j,j being an integer, less than 2.sup.n-1, and has the value 2(j-2.sup.n-1) for any value of j greater than or equal to 2.sup.n-1, so that Met.sub.r (E.sub.j) takes the larger of the values of the expressions Met.sub.r-1 (E.sub.2k)+Pr(b(r)=O/E.sub.2k) and Met.sub.r-1 (E.sub.2k+1)+Pr(b(r)=O/E.sub.2k+1).