Decision-feedback equalizer capable of producing an equalized signal at a high speed without a remaining fading

A decision-feedback equalizer for use in combination with a demodulator section for demodulating a received signal into a demodulated signal, said decision-feedback equalizer comprising:

• first filter means for filtering said demodulated signal into a first filtered signal in accordance with first through N-th primary controllable tap gains, where N represents a positive integer;
• delay means for delaying said demodulated signal during a predetermined time to produce a delayed signal;
• main filter means for filtering said delayed signal into a main filtered signal in accordance with a main controllable tap gain;
• second filter means for filtering an input signal into a second filtered signal in accordance with first through M-th subsidiary controllable tap gains, where M represents a positive number;
• first producing means for producing a third filtered signal dependent upon said first and said second filtered signals and said main filtered signal;
• second producing means for producing an equalized signal as said input signal dependent upon said third filtered signal;
• error signal producing means for producing an error signal dependent upon said equalized signal and said third filtered signal;
• (claim 1 continued)
• first generating means for generating first through N-th primary gain values dependent upon said demodulated signal and said error signal;
• main generating means for generating a main gain value dependent upon said delayed signal and said error signal;
• second generating means for generating first through M-th subsidiary gain values dependent upon said error signal and said equalized signal;
• detecting means for detecting whether or not said demodulator section is put in a synchronization state to produce a first detecting signal when said demodulator section is put in said synchronization state, said detecting means producing a second detecting signal when said demodulator section is put out of said synchronization state;
• first processing means for processing said first through said N-th primary gain values into said first through said N-th primary controllable tap gains in accordance with first through N-th primary parameters, respectively;
• main processing means for processing said main gain value into said main controllable tap gain in accordance with a main parameter;
• second processing means for processing said first through said M-th subsidiary gain values into said first through said M-th subsidiary controllable tap gains in (claim 1 twice continued) accordance with first through M-th subsidiary parameters, respectively;
• first delivering means responsive to any one of said first and said second detecting signals for delivering a main value as said main parameter to said main processing means;
• second delivering means responsive to said first detecting signal for delivering first through N-th primary values and first through M-th subsidiary values as said first through said N-th primary parameters and said first through said M-th subsidiary parameters to said first and said second processing means, respectively, and
• third delivering means responsive to said second detecting signal for delivering first through N-th additional primary values and first through M-th additional subsidiary values as said first through said N-th primary parameters and said first through said M-th subsidiary parameters to said first and said second processing means, respectively.