Decoder checking circuits suitable for semiconductor memories
AssigneeOki Electric Industry Co., Ltd.
InventorsSatoshi Ishii, Yuki Ushida
Life of this patent
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Abstract
A decoder checking circuit for testing a decoder in a semiconductor memory device, comprising an address signal generator for generating a test address signal, a first switch for transferring selectively either the address signal or the test address signal, to a decoder, a second switch for transferring the output of the decoder to the memory cell array, an expected value generator for generating an expected value for the output of the decoder, and a comparing circuit for comparing the output of the second switch with the expected value.
Claims10
A semiconductor memory with a decoder checking circuit comprising:
- a memory cell array having a plurality of memory cells;
- an address signal generator for generating a test address signal;
- a first switching means having a first input receiving an address signal, a second input receiving the test address signal, and an output, for connecting selectively the output to either the first input or the second input in response to a switching signal;
- a decoder having an input connected to the output of said first switch means and an output;
- a second switching means having an input connected to the output of said decoder, a first output connected to said memory cell array, and a second output, for connecting selectively the input to either the first output or the second output in response to the switching signal;
- an expected value generator for generating an expected value signal;
- and
- a comparing circuit for comparing a signal outputted from the first output of said second switching means with the expected value signal and outputting an error signal in accordance with the result of the comparison.
A semiconductor memory with a decoder checking circuit comprising:
- a memory cell array having a plurality of memory cells;
- an address signal generator for generating a test address signal;
- a first switching means having a first input receiving an address signal, a second input receiving the test address signal, and an output, for connecting selectively the output to either the first input or the second input in response to a switching signal;
- a decoder having an input connected to the output of said first switch means and an output;
- a second switching means having an input connected to the output of said decoder, a first output connected to said memory cell array, and a second output, for connecting selectively the input to either the first output or the second output in response to the switching signal;
- an expected value generator for generating an expected value signal;
- and
- a comparing circuit for comparing a signal outputted from the decoder with the expected value signal outputted from the expected value generator, and outputting an error signal in accordance with the result of the comparison.
Dependencies are inferred from the claim text.