Self-testing logic with embedded arrays

Abstract

Shift register latch scan strings employed in level sensitive scan design methodology for built-in circuit self-test are provided with bypassable portions which are made to serve effectively as address registers for arrays which are embedded in blocks of logic for which the scan strings are meant to provide pseudo-random excitation test data. Additionally, the bypassable portion of the scan strings is connected to an address stepper mechanism which insures complete coverage throughout the range of cell addresses within the array. This is accomplished through the utilization of a stepping counter or the utilization of an linear feedback shift register or similar mechanism. It thus becomes possible to insure that every cell address in the array is provided with known pseudo-random data at the beginning of a test and which is also capable of readily providing array cell content information at the end of the test and/or at various times during test.

Dependencies are inferred from the claim text.