Method and apparatus for frame phase conversion of signal having frame structure

A method of converting a frame phase of a signal having a frame structure which contains N (N:

• an integer 2 or above) pieces of frames applied with time-division/multiplex, comprising steps of:
• giving said N pieces of frames to N pieces of first memories, respectively;
• giving a first write address independently to said respective first memories so that said N pieces of frames are written in said respective first memories in a first write phase same as a phase in said signal;
• giving a first read address independently to said respective first memories so that said N pieces of frames are read out of said respective first memories in a first read phase same as said first write phase;
• setting a first difference between said first write and read address in said respective first memories identical under an initial state, said first difference corresponding to a difference in phase between said first write and read addresses;
• performing rereading or read skipping of a frame of a specific address of a first memory in accordance with a difference between existing first write and read addresses in each of said respective first memories;
• giving said N pieces of frames which have been read out of said respective first memories to N pieces of second memories, respectively;
• giving a second write address independently to said respective second memories so that said N pieces of frames which have been read out of said respective first memories are written in said respective second memories in a second write phase same as said first read phase;
• giving a second read address independently to said respective second memories so that said N pieces of frames are read out of said respective second memories in a second read phase same as said second write phase to said respective second memories;
• setting a second difference between said second write and read addresses in said respective second memories identical under an initial state, said second difference corresponding to a difference in phase between said second write and read addresses;
• and
• executing a justification operation for a frame which is read out of a second memory in accordance with a difference between existing second write and read addresses in said respective second memories.

An equipment for converting a frame phase of a signal having a frame structure which contains N (N:

• an integer 2 or above) pieces of frames applied with time-division/multiplex, comprising:
• N pieces of memories which store said N pieces of frames, respectively;
• a write address generating means which gives a write address independently to said respective memories so that said N pieces of frames are written in said respective memories in a write phase same as a phase in said signal;
• a read address generating means which gives a read address independently to said respective memories so that said N pieces of frames are read out of said respective memories in a read phase same as said write phase;
• means for setting a difference between said write and read addresses in said respective memories identical under an initial state, said difference corresponding to a difference in phase between said write and second addresses;
• and
• means for executing a justification operation independently from a frame which is read out of a memory in accordance with a difference between existing write and read addresses in said respective memories.

An equipment for converting a frame phase of a signal having a frame structure containing N (N:

• an integer 2 or above) pieces of frames applied with time-division/multiplex, comprising:
• N pieces of first memories which store said N pieces of frames, respectively;
• means for giving a first write address independently to said respective first memories so that said N pieces of frames are written in said respective first memories in a first write phase same as a phase in said signal;
• means for giving a first read address independently to said respective first memories so that said N pieces of frames are read out of said respective first memories in a first read phase same phase as said first write phase;
• means for setting a first difference between said first write and read addresses in respective first memories identical under an initial state, said first difference corresponding to a difference in phase between said first write and read address;
• means for performing rereading or read skipping of a frame of a specific address of a first memory in accordance with a difference between existing present first write and read addresses in said respective first memories;
• N pieces of second memories which store said N pieces of frames that have been read out of said first memories;
• means for giving a second write address independently to said respective second memories so that said N pieces of frames that have been read out of said respective first memories are written in said respective second memories in a second write phase same as said first read phase.
• means for giving a second read address independently to said respective second memories so that said N pieces of frames are read out of said respective second memories in a second read phase same as said second write phase to said respective second memories;
• means for setting a second difference between said second write and read addresses in said respective second memories identical under an initial state, said second difference corresponding to a difference in phase between said second write and read addresses;
• and
• means for executing a justification operation on a frame which is read out of a second memory in accordance with a difference between existing second write and read addresses in respective second memories.

An equipment for separating a frame phase of a signal having a frame structure containing N (N:

• a positive integer) pieces of frames applied with time-division/multiplex, comprising:
• a separating circuit which separates said signal having said frame structure into said N pieces of frames and sends them to N lines of highways, respectively;
• N pieces of first memories which store said frames on said N lines of highways, respectively;
• one piece of write control circuit which designates a common write address in writing said frames in said N pieces of first memories in accordance with a first clock;
• one piece of read control circuit which designates a common read address in reading said frames out of said N pieces of memories in accordance with a second clock;
• a phase controller which performs rereading or read skipping of a specific address of said respective first memories at a same time;
• N pieces of second memories which store said N pieces of frames that have been read out of said N pieces of first memories;
• N pieces of second write control circuits which designate write addresses in writing said frames in each of said N pieces of second memories in accordance with said second clock;
• N pieces of second read control circuits which designate read addresses in reading said frames out of said N pieces of second memories in accordance with said second clock;
• and
• justification control portions which execute a justification operation independently for output frames of respective second memories in each of said N pieces of second memories in accordance with a difference between write and read addresses given thereto, said difference corresponding to a difference in phase between said write and read addresses.

An equipment for separating a frame phase of a signal having a frame structure containing N (N:

• a positive integer) pieces of frames applied with time-division/multiplex, comprising:
• a separating circuit which separates said signal having said frame structure into said N pieces of frames and sends them to N lines of highways, respectively;
• N pieces of memories which store said frames on said N lines of highways in accordance with a first clock;
• N pieces of write control circuits which designate a write address in writing said frames in said N pieces of memories in accordance with said first clock;
• N pieces of read control circuits which designate a read address in reading said frames out of said N pieces of memories in accordance with a second clock;
• and
• justification control portions which execute a justification operation independently for output frames of respective memories in each of said N pieces of memories in accordance with a difference between write and read addresses given thereto, said difference corresponding to a difference in phase between said write and read addresses.

An equipment for separating a frame phase of a signal having a frame structure containing N (N:

• a positive integer) pieces of frames applied with time-division/multiplex, comprising:
• a first memory which receives said signal having said frame structure and stores said N pieces of frames under multiplex state;
• a first write control circuit which designates a first write address of each frame in writing said N pieces of frames successively in said first memory under a multiplex state in accordance with a first clock;
• a first read control circuit which designates a first read address of each frame in reading said N pieces of frames successively under a multiplex state out of said first memory in accordance with a second clock;
• a first phase controller which executes rereading or read skipping of a specific address for said N pieces of frames in accordance with a first difference in phase between said first write and read addresses given to said first memory;
• a second memory which stores said frames which have been read out of said first memory under a multiplex state;
• a second write control circuit which designates a second write address of each frame in writing said N pieces of frames successively under a multiplex state in said second memory in accordance with said second clock;
• a second read control circuit which designates a second read address of each frame in reading said N pieces of frames under a multiplex state out of said second memory in accordance with said second clock;
• and
• a second phase control portion which executes a justification operation on each frame in accordance with a second difference in phase between said second write and read addresses for each frame given to said second memory.

An equipment for separating a frame phase of signal having a frame structure containing N (N:

• a positive integer) pieces of frames applied with time-division/multiplex, comprising:
• a memory which receives said signal having said frame structure and stores said N pieces of frames by multi-processing;
• a write control circuit which designates a write address of each frame in writing said N pieces of frames in said memory by multi-processing in accordance with a first clock;
• a read control circuit which designates a read address in reading said signal out of said memory by multi-processing in accordance with a second clock;
• and
• a phase control portion which executes a justification operation independently in each frame in accordance with a difference between write and read addresses in each of said N pieces of frames received by said memory, said difference corresponding to a difference in phase between said write and read addresses.

An equipment for converting a frame phase of an administration unit (hereinafter referred to as AU) specified in the CCITT recommendation G. 709 which contains N (N:

• a positive integer) pieces of virtual container level 2 or level 1 (hereinafter referred to as VC-2 and VC-1, respectively) frames that are applied with time-division/multiplex, comprising:
• a memory which stores said N pieces of VC-2 or VC-1 frames by multi-processing;
• a write control circuit which designates respective write addresses in writing VC-2 or VC-1 frames in said memory by multi-processing;
• a read control circuit which indicates a read address in reading VC-2 or VC-1 frames out of said memory;
• and
• a phase control portion which obtains a difference in phase between a write address and a read address in each of VC-2 or VC-1 frames and executes a justification operation of a tributary unit-2 or a tributary unit-1 when the difference is other than a specific value.

A method of converting a frame phase of a signal having a frame structure which contains N (N:

• an integer 2 or above) pieces of frames, said method comprising the steps of:
• separating a signal into a plurality of administration unit frames of tributary unit frames each consisting of a virtual container specified in the CCITT recommendation G. 709 which is smaller than a capacity of said signal and a pointer and applying mapping;
• transmitting with multiplexing said plurality of administration unit frames or plurality of tributary unit frames on a same transmission line;
• having a plurality of administration unit frames or a plurality of tributary unit frames on the same transmission line pass through a relay transmission equipment which applies a same justification process to said plurality of administration unit frames or said plurality of tributary unit frames;
• and
• fetching said signal from said plurality of administration unit frames or said plurality of tributary unit frames on a receiving side.