DRAM variable row select
AssigneesUnited Memories, Inc., Nippon Steel Semiconductor Corporation
InventorMichael C. Parris
Life of this patent
Estimating the term…
Abstract
A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.
Claims19
A bit select circuit for an integrated circuit comprising:
- a variable bit select circuit having inputs coupled to receive a plurality of address bits and a control signal, and having an output, at least one of the address bits being blocked or passed depending on said control signal;
- and
- an address decoder coupled to receive said output of said variable bit select circuit to enable access to memory data.
A bit select circuit for a memory comprising:
- a plurality of address buffers coupled to receive a plurality of address bits including a variable bit select circuit coupled to receive at least one of the plurality of address bits and a control signal to provide an address buffer output, the at least one of the address bits being blocked or passed in response to said control signal;
- and
- an address decoder coupled to receive said address buffer output to enable access to memory data.
A bit select circuit for an integrated circuit comprising:
- a buffer circuit coupled to receive a plurality of address bits;
- a buffer latch circuit coupled to receive an output of said buffer circuit;
- a variable bit select circuit coupled to receive an output of said buffer latch circuit;
- a buffer output enable circuit coupled to receive an output of said variable bit select circuit;
- and
- an address decoder circuit coupled to receive an output of said buffer output enable circuit and to provide an output that enables access to memory data in response to the output of said variable bit select circuit.
A variable bit select circuit comprising:
- at least one selection transistor having a control electrode and a source-drain path, the control electrode of said selection transistor being coupled to a control signal, the source-drain path of the selection transistor being coupled to receive at least one address bit and being coupled to an output line, the at least one address bit being selectively coupled to the output line in response to a first state of the control signal;
- and
- at least one pull-up transistor having a control electrode and a source-drain path, the control electrode of the pull-up transistor being coupled to said control signal, the source-drain path of the pull-up transistor being coupled to receive a power supply signal and to the output line, and selectively coupling said power supply signal to the output line in response to a second state of the control signal.
A method of controlling the output of an address circuit comprising the steps of:
- passing all address bits in response to a first state of a control signal;
- blocking at least one of the address bits in response to a second state of the control signal;
- and
- substituting a signal for any of said blocked address bits.
Dependencies are inferred from the claim text.