Dynamically switchable reference voltage generator

An integrated circuit, comprising:

• first and second power-supply connections;
• first, second, and third mutually matched field-effect transistors of a first channel conductivity type;
• at least one resistive bias network, connected to first and second power-supply connections, and configured to generate first, second, and third different respective constant bias voltages therefrom, and to provide said three bias voltages to gates of said three matched field-effect transistors;
• said first transistor having a source operatively connected to a first power-supply connection;
• said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections;
• said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections;
• logic connected to control both said switches, and to turn on no more than one thereof;
• whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.

An integrated circuit, comprising:

• first and second power-supply connections;
• first, second, and third mutually matched field-effect transistors of a first channel conductivity type;
• at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors;
• said first transistor having a source operatively connected to said first power-supply connection;
• said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections;
• said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections;
• logic connected to control both said switches, and to turn on no more than one thereof;
• whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.

An integrated circuit, comprising:

• a positive power-supply connection, and a ground connection;
• first, second, and third P-channel field-effect transistors, all having substantially identical geometries;
• at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors;
• said first transistor having a source operatively connected to said power-supply connection;
• said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said power-supply connection and ground;
• at least one regulating transistor being interposed between said first and second matched transistors;
• said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said power-supply connection and ground;
• logic connected to control both said switches, and to turn on no more than one thereof;
• an N-channel output transistor connected to be controlled by a node intermediate between the channels of said first and second transistors, and accordingly to pass current from said power-supply connection to a load terminal;
• an additional series-connected pair of field-effect transistors, jointly connected in parallel with said output transistor, and including
• an additional P-channel transistor having a gate connected to the gate of said first matched transistor, and also
• an additional N-channel transistor having a gate connected to the gate of said regulating transistor;
• whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.

A circuit for the generation of reference voltages, comprising:

• a first transistor placed between a positive voltage source and an output node, and having its gate biased at a first voltage;
• one second transistor and one third transistor connected in parallel, each being identical to said first transistor, each having its gate biased at a different respective voltage and being mounted in series with a respective switching transistor between said output node and ground;
• a sequence of resistors in series between the positive voltage source and the ground to deliver different bias voltages to the gates of said first, second, and transistors;
• logic connected and configured to make only one said switching transistor conductive at a time to generate a determined level at the output of the generation stage.

An integrated circuit memory, comprising:

• an array of memory cells;
• and peripheral circuitry, including
• address decode logic connected to receive address bits and to access a correspondingly one of said cells;
• and
• control logic connected to receive one or more control bits and to select a mode of operation of said peripheral circuitry accordingly;
• reference-voltage-generating circuit, connected to receive an external voltage supply, and connected to receive bits from said control logic indicating a mode of operation, and to supply at least one reference voltage to said peripheral circuitry in dependence on said bits from said control logic;
• said reference-voltage-generating circuit comprising
• first, second, and third mutually matched field-effect transistors of a first channel conductivity type;
• at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors;
• said first transistor being operatively connected between said second transistor and said first power-supply connection;
• said second transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection;
• said third transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection;
• and
• logic connected to control both said switches, and to turn on no more than one thereof, in accordance with bits received from said control logic.

A method for generating multiple reference voltages on-chip from a single voltage externally supplied between first and second power-supply connections comprising the steps of:

• using a voltage-dividing ladder between the first and second power-supply connections to generate three different substantially constant bias voltages to the respective gates of first, second, and third mutually matched field-effect transistors of a first channel conductivity type;
• said first transistor being operatively connected between the second transistor and the first power-supply connection;
• selectably, when a first reference voltage is desired, connecting said second transistor, but not said third transistor, between said first transistor and the second power-supply connection;
• and
• selectably, when a second reference voltage is desired, connecting said third transistor, but not said second transistor, between said first transistor and the second power-supply connection;
• and
• connecting a node between said first and second transistors to provide a reference voltage which is substantially constant.