Memory control device
OwnerTsukasa Matsushita, Akira Shimataniinventors
Life of this patent
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Abstract
A memory control device for controlling writing and reading data in and from a line memory made up of a plurality of FIFO memories. Writing clocks are circularly applied to the plurality of FIFO memories of the line memory. Also, reading clocks are circularly applied to the plurality of FIFO memories. Thus, although data written in the FIFO memories are discrete, data circularly read from the plurality of FIFO memories are sequential in such order as they are written in the line memory.
Claims31
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said storage means being interposed between a first function circuit and a second function circuit and capable of storing data transferred between the first and second function circuits, said memory control device comprising:
- writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock, the reference clock being a clock for data transfer;
- means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock;
- means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories;
- means for applying a writing authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to write data;
- means for applying a reading authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to read data;
- and
- means for organizing the relations between the reading clock and the writing clock so that in response to the writing authorizing signal the first data is written in any FIFO memory where the data is first read in response to the reading authorizing signal.
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising:
- writing clock generating means for generating writing clocks for writing data in the storage means based upon a specified reference clock, said writing clock generating means including means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means;
- means for allocating and applying the writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock;
- and
- means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising:
- writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock;
- means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating reading clocks for reading data from the storage means based upon the specified reference clock, said reading clock generating means including means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means;
- and
- means for allocating and applying the reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising:
- writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock;
- means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock;
- means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories;
- and
- a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said storage means being interposed between a first function circuit and a second function circuit and capable of storing data transferred between the first and second function circuits, said memory control device comprising:
- writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock;
- means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon said reference clock;
- means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories;
- means for applying a writing authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to write data;
- means for applying a reading authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to read data;
- and
- means for organizing the relations between the reading clocks and the writing clocks so that in response to the writing authorizing signal the first data is written in any FIFO memory where the data is first read in response to the reading authorizing signal.
A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising:
- writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock;
- means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories;
- reading clock generating means for generating reading clocks different in timing from each other and equivalent in number of the number of FIFO memories constituting the storage means, based upon said reference clock;
- means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories;
- and
- a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.
A memory control device for controlling writing and reading of data in and from a plurality of storage means, wherein each storage means is interposed between a pair of function circuits connected in series, and wherein each storage means includes a plurality of FIFO memories, said memory control device comprising:
- writing clock generating means for generating a writing clock to be applied commonly to the plurality of storage means based upon a specified reference clock so as to write data in the plurality of storage means;
- means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories of each storage means so as to circularly write data in the plurality of FIFO memories of each storage means;
- reading clock generating means for generating a reading clock to be applied commonly to the plurality of storage means based upon the specified reference clock so as to read stored data from the plurality of storage means;
- and
- means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories of each storage means so as to circularly read data from the plurality of FIFO memories of each storage means.
Dependencies are inferred from the claim text.