Address multiplexed dynamic RAM having a test mode capability

An address multiplexed dynamic random access memory (RAM) having both a normal operation mode and a test mode comprising:

• a first external terminal for receiving a row address strobe (RAS) signal;
• a second external terminal for receiving a column address strobe (CAS) signal;
• a third external terminal for receiving a write enable (WE) signal;
• a fourth external terminal for receiving input data;
• external address terminals for receiving row address signals and column address signals;
• a row address buffer coupled to said external address terminals;
• and
• a column address buffer coupled to said external address terminals,
• wherein said test mode is initiated in response to said CAS signal being at a logic "low" level and said WE signal being at a logic "low" level when said RAS signal is at a transitional logic level corresponding to a falling edge;
• wherein, in said test mode, said row address buffer responds to said row address signals in response to said RAS signal being at a transitional logic level corresponding to a falling edge and said column address buffer responds to said column address signals in response to said CAS signal being at a transitional logic level corresponding to a falling edge;
• wherein, in said test mode, the same input data is written in a plurality of memory cells of said dynamic RAM which are selected on the basis of said row address signals and said column address signals when said WE signal is at a logic "low" level,
• wherein, in said test mode, a plurality of signals are read out from said plurality of memory cells on the basis of said row address signals and said column address signals when said WE signal is at a logic "high" level, and
• wherein said dynamic RAM is returned to said normal operation mode in response to said CAS signal being at a logic "low" level and said WE signal being at a logic "high" level when said RAS signal is at a transitional logic level corresponding to a falling edge.

An address multiplexed dynamic random access memory (RAM) having both a normal operation mode and a test mode comprising:

• a first external terminal for receiving a row address strobe (RAS) signal having first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• a second external terminal for receiving a column address strobe (CAS) signal having corresponding first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• a third external terminal for receiving a write enable (WE) signal having corresponding first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• external address terminals for receiving row address signals and column address signals;
• a row address buffer coupled to said external address terminals and being activated by a row address buffer timing signal produced in response to said RAS signal;
• and
• a column address buffer coupled to said external address terminals and being activated by a column address buffer timing signal produced in response to said CAS signal,
• wherein said test mode is initiated in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "0" level when said RAS signal is at a transitional logic level from that of said logic "1" level to said logic "0" level,
• wherein, in said test mode, said row address buffer responds to said row address signals in response to said RAS signal being at a transitional logic level from that of said logic "1" level to said logic "0" level and said column address buffer responds to said column address signals in response to said CAS signal being at a transitional logic level from that of said logic "1" level to said logic "0" level, and
• wherein said dynamic RAM is returned to said normal operation mode in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "1" level when said RAS signal is at a transitional logic level from that of said logic "1" level to said logic "0" level.

An address multiplexed dynamic random access memory (RAM) having both a normal operational mode and a test mode comprising:

• a first external terminal for receiving a row address strobe (RAS) signal having first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• a second external terminal for receiving a column address strobe (CAS) signal having corresponding first and second voltage levels indicative of binary levels "1" and "0", respectively;
• a third external terminal for receiving a write enable (WE) signal having corresponding first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• a fourth external terminal for receiving input data;
• external address terminals for receiving row address signals and column address signals;
• a row address buffer coupled to said external address terminals and being activated by a row address buffer timing signal produced in response to said RAS signal;
• and
• a column address buffer coupled to said external address terminals and being activated by a column address buffer timing signal produced in response to said CAS signal,
• wherein said test mode is initiated in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "0" level when said RAS is at a transitional logic level from that of said logic level "1" to said logic level "0",
• wherein, in said test mode, said row address buffer responds to said row address signals in response to said RAS signal being at a transitional logic level from that of said logic level "1" to said logic level "0" and said column address buffer responds to said column address signals in response to said CAS signal being at a transitional logic level from that of said logic level "1" to said logic level "0",
• wherein, in said test mode, the same input data is written in a plurality of memory cells of said dynamic RAM which are selected on the basis of said row address signals and said column address signals when said WE signal is at a logic "0" level;
• wherein, in said test mode, a plurality of signals are read out from said plurality of memory cells on the basis of said row address signals and said column address signals when said WE signal is at a logic "1" level;
• and
• wherein said dynamic RAM is returned to said normal operation mode in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "1" level when said RAS signal is at a transitional logic level from that of said logic level "1" to said logic level "0".

A method of testing memory cells in an address multiplexed dynamic random access memory (RAM) including a first external terminal for receiving a row address strobe (RAS) signal having first and second voltage levels indicative of binary logic levels "1" and "0", respectively;

• a second external terminal for receiving a column address strobe (CAS) signal having corresponding first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• a third external terminal for receiving a write enable (WE) signal having corresponding first and second voltage levels indicative of binary logic levels "1" and "0", respectively;
• external address terminals for receiving row address signals and column address signals;
• and row and column address buffers, coupled to said external address terminals, for providing internal row and column address signals used for accessing memory cells, said method comprising:
• initiating a test mode in said dynamic RAM in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "0" level when said RAS signal is at a transitional logic level from that of said logic "1" level to said logic "0" level;
• effecting a testing operation of said dynamic RAM by activating said row address buffer to respond to incoming row address signals in response to said RAS signal being at a transitional logic level from that of said logic "1" level to said logic "0" level and activating said column address buffer to respond to incoming column address signals in response to said CAS signal being at a transitional logic level from that of said logic "1" level to said logic "0" level;
• and
• returning said dynamic RAM to a normal operation mode from said test mode in response to said CAS signal being at a logic "0" level and said WE signal being at a logic "1" level when said RAS signal is at a transitional logic level from that of said logic "1" level to said logic "0" level.