Read circuit for accessing dynamic random access memories (DRAMS)

Access circuitry for driving serially connected pull up and pull down output transistors to generate an output logic swung which has been up converted from a smaller input logic swing, including, in combination:

• a) a level translator stage connected to receive a small pull up logic swing and operative to convert it to a larger output logic swing;
• b) applying means connected between said level translator stage and said pull up output transistor for applying an output logic swing to said pull up output transistor;
• c) an enable gate connected between said level translator stage and said pull down output transistor, whereby said enable gage is operative to turn on said pull down output transistor only after a logic swing output from said level translator stage changes levels to thereby turn off said pull up output transistor, thereby eliminating crossing current in the series circuit output connection containing said pull up and pull down output transistors;
• d) said level translator stage and said enable gate are connected, respectively, in parallel signal processing paths of a read data processing channel for a DRAM;
• and
• e) one output line from said level translator stage is connected through the applying means to said pull up output transistor and another output line from said level translator stage is connected through an inverter and then through a logic gate where an inverted signal is combined with an input signal to said level translator stage, and an output line from said logic gate is connected as one input to said enable gate, whereby an output signal from said enable gate may be inverted and applied to said pull down output transistor.

A dynamic random access memory device, comprising:

• a) an output driver, having a pull-up circuit, a pull-down circuit, and an output node;
• b) an output buffer for accepting a pull-up condition and a pull-down condition, said output buffer electrically coupled to the output driver;
• c) a level translator located in the output buffer and responding to the pull-up and pull down conditions to generate a level translator signal at a level translator output node, said level translator signal coupled to said pull-up circuit;
• and
• d) a timing device located in the output buffer and having an input node coupled to said level translator output node and having a first output node electrically coupled to the pull-up circuit and having a second output node electrically coupled to the pull-down circuit, said timing device responding to said level translator signal to generate a first timing signal at said first output node to deactivate said pull-up circuit thereby terminating a driving of a first potential to said output node of said output driver and responding to said level translator signal to generate a second timing signal at said second output node to activate said pull-down circuit thereby driving said output node of said output driver to a second potential, said timing device timing a generation of said first and said second timing signals such that said pull-up circuit is deactivated prior to said pull-down circuit being activated.

A dynamic random access memory device, comprising:

• a) an output driver having a pull-up device, a pull-down device, and an output node interposed between said pull-up device and said pull-down device, a first potential driven to said output node through said pull-up device in response to an active pull-up signal on a control input of said pull-up device and in response to an inactive pull-down signal on a control input of said pull-down device, a second potential driven to said output node through said pull-down device in response to an inactive pull-up signal on said control input of said pull-up device and in response to an active pull-down signal on said control input of said pull-down device;
• b) a control circuit in electrical communication with said output device circuit, wherein said control circuit generates said active and inactive pull-up control signals and generates said active and inactive pull-down signals, said control circuit accepting a first data signal at a first input and a second data signal at a second input;
• and
• c) a level translator circuit, an output of said level translator circuit in electrical communication with a third input of said control circuit, said level translator circuit accepting said first data signal and generating a level translated signal to said control circuit at said third input, wherein said active pull-up signal is generated in said control circuit in response to a said first data signal having a first logic state and in response to said level translated signal, and wherein said inactive pull-down signal is generated in said control circuit in response to said second data signal having a second logic state, and wherein said inactive pull-up signal is generated in said control circuit in response to said first data signal having a second logic state and in response to said level translated signal and wherein said active pull-down signal is generated in said control circuit in response to said first data signal having said second logic state, in response to said level translated signal and in response to said second data signal having said first logic state, said control circuit controlling a timing of the generation of said inactive pull-up signal and said active pull-down signal such that said active pull-up signal becomes inactive before said inactive pull-down signal becomes fully active.