Orthogonal transformation processor for compressing information

An orthogonal transformation processor comprising:

• an orthogonal transformation circuit for dividing one image into blocks including a plurality of picture elements and performing an orthogonal transformation processing every block using a ROM table;
• an address generator disposed in the orthogonal transformation circuit and responsive to input data received one bit at a time and transformation coefficient data of plural bits to generate data indicative of an address of said ROM table to cause said ROM table to output data therefrom;
• an adding circuit receiving data read out of the ROM table and providing output data;
• a register disposed in the orthogonal transformation circuit to receive and hold the output data provided by the adding circuit;
• and
• a one-bit shifter disposed in the orthogonal transformation circuit to receive and shift a bit position of the data held in the register in the direction of an upper or a lower position in accordance with a bit position of the input data inputted to said address generator to thereby provide shifted data;
• said adding circuit receiving said shifted data and adding the data read out of the ROM table and the shifted data to provide said output data for each one of the bits of the input data received by said address generator.

A method of performing an orthogonal transformation comprising the steps of:

• dividing an image into blocks including a plurality of picture elements and performing an orthogonal transformation processing every block using a ROM table;
• generating data indicative of an address of said ROM table in response to input data received one bit at a time and transformation coefficient data of plural bits to cause said ROM table to output data therefrom;
• receiving the data read out of said ROM table and providing output data in response thereto;
• holding said output data in a register;
• and
• shifting a bit position of the data held in the register in a direction of an upper or lower position in accordance with a bit position of the input data of said address to thereby provide shifted data;
• wherein the output data is obtained by receiving said shifted data and adding the data read out of the ROM table and the shifted data to provide said output data for each one of the bits of the input data.