US 5,331,538 AGranted

Mail processing system controller

AssigneePitney Bowes Inc.

InventorsPeter C. DiGiulio, Michael L. Ernandez, Frank D. Ramirez, Mark W. Van Gorp

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Abstract

The processing system controller is utilized in a mail processing system. The processing system controller provides process control over a plurality of processing subsystems which operate on a mailpiece traversing the processing system. The processing subsystems employing a plurality of prime movers controlled by the processing controller. The processing system controller includes a motor controller in bus communication with the prime movers for control of the prime movers. Sensors monitor the operating conditions and parameter of each subsystems and are in bus communication with a sensor controller. A random access memory (RAM) is in bus communication with the motor controller and the sensor controller. The motor controller and the sensor controller are programmed such that the motor controller can read from the RAM and the sensor controller can write to the RAM. The motor controller reads from the RAM at discrete time intervals and the sensor controller writes to the RAM at other discrete time intervals.

Claims5

Dependent claims

A controller system for providing process control by controlling the operation of a plurality of machine modules to carry out a plurality of programmed processes, each of said machine modules having a plurality of subsystems for executing respective process functions, said controller system comprising:

a first system controller means for controlling a first machine module subsystems common to respective ones of said plurality machine modules in accordance with programming for said respective machine modules in response to a plurality of selectable machine parameters and process parameters;
a second system controller means for controlling a second machine module subsystem common to respective ones of said plurality of machine modules in accordance with programming for said respective machine modules in response to a plurality of selectable machine parameter and process parameters;
a data bus, said first and second system controller having microprocessor means for transmitting process parameters on said data bus and accessing process parameters along said data bus;
shared memory means having a memory unit, said memory unit having plurality of first addressable registers for storing said process parameters, and having a shared memory controller means for providing said first system controller access over said data bus for access to said first addressable registers bysaid memory unit during a first time interval and for providing said second controller access over said data bus for access to said first addressable registers of said memory during a second time interval said first controller microprocessor means being programmed to restrict said first controller microprocessor read only data from said first registers of said memory unit, and said second controller microprocessor means being programmed to restrict said second controller microprocesor to write only data to said first registers of said memory unit;
a host controller having microprocessor means for transmitting processor parameters over said data bus;
said memory unit having a plurality of second addressable registers for storing said machine parameters;
said shared memory controller means for further providing said host system controller access to said data bus for access to said first addressable registers of said memory unit during a third time interval;
said host controller microprocessor being programmed to access said first ones of said addressable registers of said memory at a third time interval by said shared memory means;
said first and second controllers being further programmed to read from and write to said second ones of said registers of said memory unit.

6 more elements

A processing system controller for controlling the operation of a plurality of machine modules to carry out a plurality of programmed processes, each of said machine modules having a plurality of subsystem for executing respective process functions, said controlled system comprising:

a motor controller means for actuating respective prime movers of said respective machine modules in response to said machine parameters and for controlling the respective prime movers of said respective machine modules in accordance with programming for said respective machine modules in response to a plurality of selectable machine parameters and process parameters;
sensing means for selectively and continuously sensing said respective machine module status and generating state signals in response thereto;
a sensor controller means for receiving said state signals and generating process parameter and for actuating said sensing means in accordance with select ones of said machine parameters;
a host system controller means for controlling ancillary process functions;
a data bus, said motor, sensor and host system controllers having microprocessor means for transmitting process parameters on said data bus and accessing process parameters along said data bus;
shared memory controller means for providing said motor controller an sensor controller access to read from and write to select ones of said registers by said shared memory means at said respective first and second time intervals;
shared memory means having a memory unit, said memory unit having a plurality of first and second addressable registers for storing said parameters wherein said shared memory controller means is programmed to provide said motor controller access to said data bus for access to said addressable registers of said memory unit during a first time interval, for providing said sensor controller access to said data bus for access to said addressable registers during a second time interval (c) for providing said host controller access to said data bus for access to a said addressable registers or said memory unit during a third time interval;
and,
said motor controller microprocessor means being programmed to restrict said motor controller microprocessor to read data from only said first registers of said memory unit, and to read data from and write data to said second registers of said memory unit;
said senor controller microprocessor means being programmed to restrict said second controller microprocessor to write data only to said first registers of said memory unit, and to read data from and write data to said second registers of said memory unit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/034,198Filed 19 Mar 1993 · continuation in part
Priority: 23 Oct 1989
Granted: 19 Jul 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G05B 19/4147
Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller:…
G05B 19/0421
Using digital processors: multiprocessor system
G05B 2219/25369
Pc structure of the system: control of states, real time
G05B 2219/25431
Pc structure of the system: dual Port memory