Autoranging phase-lock-loop circuit

An autoranging phase-lock-loop circuit for locking the output of a voltage controlled oscillator onto a reference frequency, the autoranging phase-lock-loop circuit comprising:

• range programmable voltage controlled oscillator means for generating a current oscillator output signal in response to one of a plurality of range select signals, each range select signal corresponding to a range of oscillator output frequencies, and for varying a frequency of the current oscillator output signal in response to a loop filter voltage;
• counter means for generating a first enable signal a preselected settling time after receiving a reset signal, for removing the first enable signal a preselected turn-off time after generating the first enable signal if the counter means has not received a subsequent reset signal since a most recent first enable signal was generated, and for generating a second enable signal after removing the first enable signal;
• phase error detector means for comparing the current oscillator output signal to a reference signal in response to the first enable signal, for generating a shift signal and the reset signal if a phase error is detected, the reset signal being generated a delay time after the shift signal, and for suspending a comparison of the current oscillator output signal to the reference signal when the first enable signal is removed;
• shift register means for selecting a next range of oscillator output frequencies in response to the shift signal by generating a new range select signal from the plurality of range select signals;
• phase comparator means for comparing the current oscillator output signal to the reference signal and for generating a difference signal in response thereto;
• and
• loop filter means for generating the loop filter voltage in response to the difference signal.