Sense amplifier circuit for reducing transmission delay in data line
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Urakawa
Life of this patent
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Abstract
A plurality of differential amplifier circuits are supplied with respective potentials of a plurality of paired bit lines and subjects the potentials of the bit line pairs to the differential amplification. The plurality of differential amplifier circuits are connected to paired data lines. The paired data lines are connected at one end to a first clamping circuit for clamping the potential of the paired data lines. The first clamping circuit is connected to a common load circuit acting as a common load for the plurality of differential amplifier circuits. The paired data lines are connected at the other end to a second clamping circuit for reducing the amplitude of a voltage between the paired data lines.
Claims19
A sense amplifier circuit comprising:
- a plurality of differential amplifier means for receiving potentials of a plurality of pairs of bit lines at input terminals thereof and subjecting the potentials of the bit line pairs to a differential amplification;
- common load means acting as a common load for said plurality of differential amplifier means;
- paired data lines connected to said plurality of differential amplifier means;
- first clamping means connected between said common load means and said paired data lines, for clamping the potentials of said paired data lines;
- and
- second clamping means for reducing the amplitude of a voltage between said paired data lines.
A sense amplifier circuit comprising:
- a plurality of first amplifier means for receiving potentials of a plurality of pairs of bit lines at input terminals thereof and subjecting the potentials of the bit line pairs to a differential amplification;
- paired data lines connected to said plurality of first amplifier means;
- second amplifier means connected to said paired data lines, for amplifying the potential which is subjected to the differential amplification by said plurality of first amplifier means and then output to said paired data lines;
- and
- clamping means for reducing the amplitude of a voltage between said paired data lines;
- wherein said clamping means includes detection means for detecting the amplitude of a voltage between said paired data lines;
- and controlled type current source means for controlling an amount of current flowing in said paired data lines in response to an output of said detecting means to prevent the amplitude of the voltage between said paired data lines from being increased.
Dependencies are inferred from the claim text.