CMOS/ECL signal level converter

A signal level converter for converting CMOS input signal levels to ECL output signal levels, comprising:

• first and second transistors having bases and having collectors and emitters defining collector-to-emitter paths, the emitters of said first and second transistors being connected to each other, the collector of said first transistor being directly connected to a first supply voltage potential, a first controllable resistor connected between the collector of said second transistor and the first supply voltage potential, the base of said second transistor being connected to a reference potential, and said first resistor having a control electrode;
• a third transistor having a base and having a collector and an emitter defining a collector-to-emitter path, the collector of said third transistor being connected to the emitters of said first and second transistors, a second resistor connected between the emitter of said third transistor and a second supply voltage potential, and the base of said third transistor being connected to a control potential;
• a fourth transistor having a collector connected to the first supply voltage potential, a base connected to the collector of said second transistor and an emitter;
• an input signal terminal connected to the base of said first transistor, an output signal terminal connected to the emitter of said fourth transistor;
• an inverter having an input terminal and an output terminal, said input terminal of said inverter being connected to said input signal terminal, said output terminal of said inverter being connected to said control electrode of said controllable resistor;
• said first controllable resistor having a first ohmic resistor and a first MOS transistor with a drain-to-source path forming a parallel circuit with said first ohmic resistor and a gate electrode forming said control electrode of said first controllable resistor;
• a second controllable resistor having a control electrode connected to said input signal terminal and having a second ohmic resistor and a second MOS transistor with a drain-to-source path forming a parallel circuit with said second ohmic resistor and with a gate electrode forming said control electrode of said second controllable resistor;
• a fifth transistor having a collector connected to the base of said fourth transistor, an emitter connected through said second controllable resistor to the second supply voltage potential and a base connected to a further control potential;
• third and fourth MOS transistor having drain and source terminals defining drain-to-source paths being connected in a series circuit at a connecting point, the source terminal of said third MOS transistor being connected to the first supply voltage potential, the source terminal of said fourth MOS transistor being connected to the second supply voltage potential;
• the gate electrode of said first MOS transistor being connected to the gate electrode of said third MOS transistor;
• the gate electrode of said second MOS transistor being connected to the connecting point between said third and fourth MOS transistors;
• and
• the gate and drain electrodes of said fourth MOS transistor being connected to one another.