Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line

A programmable logic device (PLD), consisting of:

• a) means, having an input and output, for creating a sum of products signal on its output;
• b) an I/O pad, having:
• b1) an input for receiving the sum-or-products signal and outputting it from the PLD, and
• b2) an output for receiving external signals, from outside of the FPLD, and inputting them;
• c) first switching means,
• having an input that is coupled exclusively and directly to the output of the creating means and an output coupled directly to the I/O pad,
• for initiating a stopping mode that prevents the sum-of-products signal from reaching the I/O pad, and
• for initiating an allowing mode that allows the sum-of-products signal to proceed to the I/O pad and be output from the PLD;
• d) internal feedback means,
• coupled at one end exclusively and directly 1) to the output of the creating means, and 2) to the input to the first switching means,
• for feeding back the sum-of-products signal to the input of the creating means;
• e) external feedback means,
• coupled at one end exclusively and directly 1) to the output of the first switching means, and 2) to the input to the I/O pad,
• for feeding back the external signals, received from the I/O pad, to the input of the creating means;
• f) second switching means,
• coupled directly to external feedback means to receive the external signals from the external feedback means, and
• coupled directly to the internal feedback means to receive the sum-of-products signals from the producing means,
• for initiating a stopping mode that prevents the sum-of-products signal from reaching the input of the producing means, but allows the external signal to reach the input of the producing means, and
• for initiating an allowing mode that allows the sum-of-products signal to proceed to the input of the producing means, but stops the external signal from reaching the input of the producing means;
• and
• g) control means,
• coupled directly to the first and second switching means,
• for initiating stopping and allowing modes of the first and second switching means.

A PLD, comprising:

• a) an AND array, being programmable, for creating product signal terms;
• b) an OR array, being programmable, receiving a portion of said product signal terms, and thereby creating a sum-of-products signal term that is outputted over a single output line;
• c) an input/output pad having an input line receiving signal terms from the OR array and having an output line for outputting those signals;
• and
• d) a macrocell means consisting of:
• d1) gating means, directly receiving OR array signal output line,
• 1) for, first, gating the sum-of-products signal term, and sending the signal term directly to the input line of the input/output pad, and
• 2) for, second, gating to prevent the sum-of-products signal term from reaching the input line to the input/output pad;
• d2) an exclusive external signal input line for routing signals, external to the FPLD, to the AND array when the FPLD is in the first gating;
• whereupon this in turn allows for an external signal to be routed into the programmable logic device over the input/output pad and along an exclusive input line,
• d3) feedback gating means, coupled to receive the external signal and the first sum-of-products signal, and
• for gating either the external or sum-of-products signal to an input to the AND array;
• d4) enable means, having;
• 1) a first output signal coupled to the gating means, and, 2) the same first output signal coupled to the feedback gating means,
• for enabling or disabling the gating means, and
• for enabling or disabling the feedback gating means to determine if the first sum-of-product signal or that an external signal will be fed back to the AND array.

A PLD, comprising:

• a) an AND array, being programmable, for creating product signal terms;
• b) an OR array, being programmable, receiving a portion of said product signal terms, and thereby creating a sum-of-products signal term that is outputted over a single output line;
• c) an input/output pad having an input line receiving signal terms from the OR array and having an output line for outputting those signals;
• and
• d) a macrocell means consisting essentially of:
• d1) gating means (34), directly receiving OR array signal output line;
• 1) for, first, gating the sum-of-products signal term, and sending the signal term directly to the input line of the input/output pad, and
• 2) for, second, gating to prevent the sum-of-products signal term from reaching the input line to the input/output pad;
• d2) an exclusive external signal input line for routing signals, external to the FPLD, to the AND array when the FPLD is in the first gating;
• whereupon this in turn allows for an external signal to be routed into the programmable logic device over the input/output pad and along an exclusive input line;
• d3) feedback gating means, coupled to receive the external signal and the first sum-of-products signal for gating either the external or sum-of-products signal to an input to the AND array;
• and
• d4) enable means, having:
• 1) a first output signal coupled to the gating means, and, 2) the same first output signal coupled to the feedback gating means,
• for enabling or disabling the gating means;
• and
• for enabling or disabling the feedback gating means to determine if the first sum-of-products signal or that an external signal will be fed back to the AND array.