US 5,331,224 A · I.sub.cct leakage current interrupter

Abstract

An electronic switch to be used in BiCMOS circuitry when CMOS stages are controlled by logic output from (bipolar) TTL stages. Its purpose is to avoid the static leakage current I.sub.cct which can occur in a CMOS stage when the pulldown transistor is turned on while the pullup transistor is not completely turned off. This is a problem which arises when CMOS and TTL stages are coupled; the logic-high output from a TTL stage is sufficient in magnitude to turn on the CMOS pulldown transistor but not to turn off the CMOS pullup transistor. The present invention introduces an ancillary input to the subcircuit encompassing the CMOS input stage and also an ancillary output from one of the CMOS stages of the subcircuit (typically an output buffer) encompassing the TTL output stage. The ancillary output is chosen so as to provide a CMOS logic-high signal whenever the TTL stage is outputting a TTL logic-high signal. The ancillary input is connected to the control node of a switching transistor interposed between V.sub.cc and the CMOS input stage's pullup transistor. In this manner, the source of I.sub.cct is interrupted immediately after the CMOS stage is switched from pull-up mode to pull-down mode. The invention has particular applicability to latched transceivers, where the CMOS input stage is located in the latch circuit and the TTL in the tristate output buffer circuit.

Claims15

Dependent claims

A BiCMOS circuit and switching means for halting static leakage current I.sub.cct in CMOS input stages controlled by bipolar logic, said BiCMOS circuit comprising a CMOS input stage and a CMOS control stage

wherein said CMOS input stage includes a CMOS input node, a PMOS pullup transistor having a pullup control gate, and an NMOS pulldown transistor comprising a pulldown control gate,
wherein said pullup control gate and said pulldown control gate are coupled in common to said CMOS input node,
wherein a drain node of said PMOS pullup transistor is coupled directly to a drain node of said NMOS pulldown transistor, and
wherein a source node of said NMOS pulldown transistor is coupled directly to a low-potential power rail,
wherein said CMOS control stage is an invertor stage included in said BiCMOS circuit and coupled between said high-potential power rail and said low-potential power rail,
wherein said switching means for halting I.sub.cct static high leakage current includes a PMOS disconnect transistor and a plurality of isolation/amplification buffers in series
wherein a disconnect control gate of said PMOS disconnect transistor is coupled to an output node of said CMOS control stage through said plurality of isolation/amplification buffers in series, and a source node of said PMOS pullup transistor is coupled to a high-potential power rail through said PMOS disconnect transistor,
wherein said plurality of isolation/amplification buffers in series is of such a number as to ensure an even number of inversions between said output node of said CMOS control stage and said disconnect control gate while providing isolation necessary to avoid loading down said output node of said CMOS control stage.

5 more elements

A BiCMOS latched transceiver circuit comprising

(a) a first data latch circuit,
(b) a first BiCMOS three-state output buffer,
(c) a second data latch circuit,
(d) a second BiCMOS three-state output buffer,
(e) a first latched transceiver I/O node, and
(f) a second latched transceiver I/O node,
wherein said first data latch circuit is coupled between a high-potential power rail and a low-potential power rail and has a first data input node coupled directly to said first latched transceiver I/O node, a first data latch CMOS input stage, a first latch intermediate stage, a first invertor loop, and a first latch output node,
wherein said first data latch CMOS input stage includes a first latch input pullup transistor coupled to said high-potential power rail through a first disconnect transistor comprising a first disconnect control gate node coupled to a first ancillary input of said first data latch circuit,
wherein said first BiCMOS three-state output buffer is coupled between said high-potential power rail and said low-potential power rail and includes (1) a first CMOS input stage having an output coupled through a plurality of invertor stages to a first CMOS control stage, and (2) a TTL output stage coupled to a first BiCMOS three-state output buffer output node,
wherein said first CMOS control stage includes a first CMOS control stage output node coupled to a first ancillary output,
wherein said second data latch circuit is coupled between said high-potential power rail and said low-potential power rail and includes a second data input node coupled directly to said second latched transceiver I/O node, a second data latch CMOS input stage, a second latch intermediate stage, a second invertor loop, and a second latch output node,
wherein said second data latch CMOS input stage includes a second data latch input pullup transistor coupled to said high-potential power rail through a second disconnect transistor having a second disconnect input node coupled to a second ancillary input of said second data latch circuit,
wherein said second BiCMOS three-state output buffer is coupled between said high-potential power rail and said low-potential power rail and includes a second CMOS input stage, a plurality of second CMOS invertor stages, a second CMOS control stage separated from said second CMOS input stage by an odd number of said plurality of second CMOS invertor stages and having a second CMOS control stage output node which is coupled to a second ancillary output,
wherein said first ancillary output of said first BiCMOS three-state output buffer is connected to said second ancillary input of said second data latch circuit and said second ancillary output of said second BiCMOS three-state output buffer is connected to said first ancillary input of said first data latch circuit, and wherein an output node of said second BiCMOS three-state output buffer is connected to said first latched transceiver I/O node and said first BICMOS three-state output buffer is connected to said second latched transceiver I/O node wherein said first latch output node of said first data latch is connected to an input of said first CMOS input stage of said first BiCMOS three-state output buffer and said second latch output node of said second data latch is connected to an input of said second CMOS input stage of said second BiCMOS three-state output buffer.

11 more elements

An I.sub.cct -minimizing improvement to a BiCMOS latched tranceiver comprising

(a) a first data latch coupled between a high-potential power rail and a low-potential power rail,
(b) a second data latch coupled between said high-potential power rail and said low-potential power rail,
(c) a first three-state buffer coupled between said high-potential power rail and said low-potential power rail, and
(d) a second three-state buffer coupled between said high-potential power rail and said low-potential power rail,
wherein said first data latch includes a first data input node coupled to a first CMOS input invertor stage, and a first data output node, wherein said second data latch includes a second data input node coupled to a second CMOS input invertor stage, and a second data output node,
wherein said first three-state buffer includes a first buffer CMOS input invertor stage coupled into a first buffer intermediary CMOS invertor stage, and a first bipolar output stage coupled to a first buffer output node, wherein said second three-state buffer includes a second buffer CMOS input invertor stage coupled into a second buffer intermediary CMOS invertor stage, and a second bipolar output stage coupled directly to a second buffer output node,
wherein said first buffer output node is connected to said second data input node, and wherein said second buffer output node is connected to said first data input node,
wherein said first data output node is connected to said first buffer CMOS input invertor stage and said second data output node is connected to said second buffer CMOS input invertor stage
said improvement comprising
(a) a first PMOS disconnect transistor interposed between said first CMOS input invertor stage and said high-potential power rail, wherein said first PMOS disconnect transistor includes a first PMOS disconnect control gate node,
(b) a second buffer ancillary output node coupled through two CMOS invertor stages in series to an output node of a second buffer control stage wherein said second buffer control stage includes said second buffer intermediary CMOS invertor stage,
(c) a direct connection between said second buffer ancillary output node and said first PMOS disconnect control gate node,
(d) a second PMOS disconnect transistor interposed between said second CMOS input invertor stage and said high-potential power rail, wherein said second PMOS disconnect transistor includes a second PMOS disconnect control gate node,
(e) a first buffer ancillary output node coupled through two CMOS invertor stages in series to an output node of a first buffer control stage wherein said second buffer control stage includes said first buffer intermediary CMOS invertor stage,
(f) a direct connection between said first buffer ancillary output node and said second PMOS disconnect control gate node.

12 more elements

Dependencies are inferred from the claim text.

I.sub.cct leakage current interrupter

Life of this patent

I.sub.cct leakage current interrupter

Life of this patent

Abstract

Claims15