Cochlear filter bank with switched-capacitor circuits

A bi-phasic operated switched-capacitor sum-gain amplifier (SGA) that includes in the bi-phasic operation a sampling interval and reset interval during each cycle of operation of the SGA, a switching circuit network that controls the charge and discharge of capacitors within the SGA,

• whereby a sampling switching circuit means within the SGA are closed during the sampling interval and open during the reset interval, and a reset switching circuit means within the SGA are open during the sampling interval and closed during the reset interval, the SGA comprises:
• an operational amplifier with an inverting terminal and an output terminal, the output terminal connects to a first reset switching circuit means;
• an input array of switched-capacitors which includes a first array of input switched-capacitors and a second array of input switched-capacitors;
• the first array of input switched-capacitors with sampling-reset switching circuit means for connecting multiple input signals to the inverting terminal during the sampling interval and to a ground during the reset interval;
• the second array of input switched-capacitors with sampling-reset switching circuit means for i) connecting additional multiple input signals to a first sampling-reset switching circuit means during the sampling interval and ii) connecting to the ground during the reset interval;
• the first sampling-reset switching circuit means effects connection to the inverting terminal of the operational amplifier during the reset interval and the ground during the sampling interval;
• a feedback circuit which includes a first feedback switched-capacitor and a second feedback switched-capacitor;
• the first feedback switched-capacitor with a second sampling-reset switching circuit means for connecting between the inverting terminal and the output terminal of the operational amplifier,
• wherein the second sampling-reset switching circuit means effects connection to the inverting terminal of the operational amplifier during the sampling interval and the ground during the reset interval;
• and
• the second feedback switched-capacitor with a third sampling-reset switching circuit means for connecting between the inverting terminal and the output terminal of the operational amplifier,
• wherein the third sampling-reset switching circuit means for connecting the inverting terminal of the operational amplifier during the reset interval and the ground during the sampling interval.

A bi-phasic, area efficient switched-capacitor sum-gain amplifier (SGA) comprises in the bi-phasic operation a sampling interval and reset interval during each cycle of operation of the SGA, a switching circuit network that controls the charge and discharge of capacitors within the SGA,

• whereby a sampling switching circuit means within the SGA are closed during the sampling interval and open during the reset interval, and a reset switching circuit means within the SGA are open during the sampling interval and closed during the reset interval, the SGA comprises:
• an operational amplifier with an inverting terminal and output terminal, the output terminal connects to a first reset switching circuit means;
• an input array of switched-capacitors which includes a first array of input switched-capacitors and a second array of input switched-capacitors;
• the first array of input switched-capacitors with sampling-reset switching circuit means for connecting multiple input signals to a first common connection that includes a first feedback switched-capacitor circuit and a first sampling-reset switching circuit means, the first sampling-reset switching circuit means in turn connects to the inverting terminal through a second common connection formed by a second feedback switched-capacitor circuit,
• wherein during the sampling interval, the first array of capacitors are connected to the inverting terminal, and during the reset interval, the first array connects to a ground;
• the second array of input switched-capacitors with sampling-reset switching circuit means connects additional multiple input signals to the first common connection,
• wherein during the reset interval, the second array of switched-capacitors connects to the ground through the first sampling-reset switching circuit means, and during the sampling interval, the second array's input signals disconnects from the SGA;
• the first feedback switched-capacitor circuit includes a first capacitor with a first terminal and a second terminal, the second terminal of the first capacitor connects to the first common connection, the first terminal of the first capacitor connects to a second sampling-reset switching circuit means which in turn connects to the output terminal of the operational amplifier,
• wherein during the sampling interval, the first feedback switched-capacitor circuit connects between the inverting terminal and the output terminal of the operational amplifier and during the reset interval, the first capacitor's first terminal connects to the ground through the second sampling-reset switching circuit means;
• the second feedback switched-capacitor circuit includes a second capacitor and a third capacitor each with a first terminal and a second terminal, the second and third capacitor's second terminal connects to a third sampling-reset switching circuit means, the second capacitor's first terminal connects to the first capacitor's first terminal, the third capacitor's first terminal connects through a fourth sampling-reset switching circuit means to the output terminal of the operational amplifier,
• wherein during the sampling interval, the second and third capacitor's second terminal connects to the ground, the second capacitor's first terminal connects to the operational amplifier's output terminal through the second sampling-reset switching circuit means to the ground through the fourth sampling-reset switching circuit means, and during the reset interval, the third capacitor connects between the inverting terminal and the output terminal of the operational amplifier.

An area-efficient offset-compensated bi-phasic operated switched-capacitor sum-gain amplifier (SGA) comprises in the bi-phasic operation a sampling interval and reset interval during each cycle of operation of the SGA, a switching circuit network that controls the charge and discharge of capacitors within the SGA,

• whereby a sampling switching circuit means within the SGA are closed during the sampling interval and open during the reset interval, and a reset switching circuit means within the SGA are open during the sampling interval and closed during the reset interval, the SGA comprises:
• an operational amplifier with an inverting terminal and output terminal, the output terminal connects to a first reset switching circuit means;
• an input array of switched-capacitors which includes a first array of input switched-capacitors and a second array of input switched-capacitors;
• the first array of input switched-capacitors with sampling-reset switching circuit means connects multiple input signals to a first common connection that includes a first feedback switched-capacitor circuit and a second reset switching circuit means and an offset storage capacitor, the offset storage capacitor in turn connects to the inverting terminal of the operational amplifier through a second common connection formed by common connection with a second feedback switched-capacitor circuit,
• wherein during the sampling interval, the first array of capacitors connects to the inverting terminal of the operational amplifier through the offset storage capacitor, and during the reset interval, the first common connection connects to a ground through the second reset switching means and the multiple input signals connects to the ground through the first switched-capacitor array;
• the second array of input switched-capacitors with sampling-reset switching circuit means connects additional multiple input signals to the first common connection,
• wherein during the reset interval, the second array of switched-capacitors connects to the ground through the second reset switching circuit means, and during the sampling interval, the multiple input signals are disconnected from the second array;
• the first feedback switched-capacitor circuit includes a first capacitor with a first terminal and a second terminal, the second terminal of the first capacitor connects to the first common connection, the first terminal of the first capacitor connects to a second sampling-reset switching circuit means which in turn connects to the output terminal of the operational amplifier,
• wherein during the sampling interval, the first feedback switched-capacitor circuit connects between the inverting terminal and the output terminal of the operational amplifier and during the reset interval, the first capacitor's first terminal connects to the ground through the second sampling-reset switching circuit means;
• the second feedback switched-capacitor circuit includes a second capacitor and a third capacitor each with a first terminal and a second terminal, the second and third capacitor's second terminal connects to a third sampling-reset switching circuit means, the second capacitor's first terminal connects to the first capacitor's first terminal, the third capacitor's first terminal connects through a fourth sampling-reset switching circuit means to the output terminal of the operational amplifier,
• wherein during the sampling interval, the second and third capacitor's second terminal connects to the ground, the second capacitor's first terminal connects to the operational amplifier's output terminal through the second sampling-reset switching circuit means to the ground through the fourth sampling-reset switching circuit means, and during the reset interval, the third capacitor connects between the inverting terminal and the output terminal of the operational amplifier.