US 5,331,215 A · Electrically adaptable neural network with post-processing circuitry · patentgrep

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Abstract

A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.

Claims44

Dependent claims

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, a MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
at least one column sense line associated with each column of said array, each column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column, and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column;
and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

3 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, first negative feedback means coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, second negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said Synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column;
and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

3 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said inverter, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column;
and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

3 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said inverter, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a Signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column;
and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

3 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said inverter, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said inverter, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for Supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column;
and
an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

3 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, first negative feedback means coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, second negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;
a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;
a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;
and
a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/922,535Filed 30 Jul 1992 · continuation in part
Priority: 9 Dec 1988
Granted: 19 Jul 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03F 1/303
Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters: using a switching device
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
H03F 1/0261
In transistor amplifiers: with control of the polarisation voltage or current, e.g. gliding Class A
H03F 3/45479
With semiconductor devices only: characterised by the way of common mode signal rejection

Family

Serial282,176Parent of this continuation-in-part · filed 9 Dec 1988
Serial486,336Parent of this continuation-in-part · filed 28 Feb 1990
Serial525,764Parent of this continuation · filed 18 May 1990
Serial781,503Parent of this continuation-in-part · filed 22 Oct 1991
Serial913,691Parent of this continuation-in-part · filed 14 Jul 1992
US 5,160,899 AParent of this continuation-in-part
US 5,059,920 AParent of this continuation
US 5,068,622 AParent of this continuation-in-part
US 4,935,702 AParent of this continuation-in-part
US 5,331,215 AThis patent

From the US filing history. Foreign family members aren’t listed.

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