Semiconductor memory device including gate electrode sandwiching a channel region

A semiconductor memory device comprising:

• a plurality of memory cells each of which includes:
• an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions that sandwich said channel region therebetween;
• and an electrically breakable memory element provided on one of said main electrode regions, wherein a doped semiconductor region is provided between said opposing portions beneath said channel region, said doped semiconductor region having a same conductivity type as said channel region and an impurity concentration higher than that of said channel region, and
• wherein said plurality of memory cells are matrix connected by a first interconnection which is common to the gate electrodes of said memory cells and a second interconnection which is common to the memory elements of said memory cells, a power source line being disposed between said second interconnections.