Non-volatile DRAM cell

A non-volatile dynamic random access memory cell comprising:

• a semiconductor substrate;
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a transfer transistor disposed between said storage node and said source diffusion region;
• and
• a floating gate formed in said layer of insulating material between said control electrode and said surface of said semiconductor substrate, said floating gate having a first layer disposed over said storage node and separated therefrom by said insulating material having a thickness that will allow electrons to tunnel between said storage node and said first layer for transferring a charge directly between said floating gate and said storage capacitor, and a second layer disposed at a greater distance from said surface of said semiconductor substrate than said first layer, said first layer being connected to said second layer;
• and
• an erase gate formed in said layer of insulating material above said first layer of said floating gate.

A non-volatile dynamic random access memory cell comprising:

• a semiconductor substrate;
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a transfer transistor disposed between said storage node and said source diffusion region;
• and
• a floating gate formed in said layer of insulating material above said surface of said semiconductor substrate, a portion of said floating gate being disposed over said storage node and separated therefrom by a dual electron injector structure for transferring a charge directly between said floating gate and said storage capacitor.

A non-volatile dynamic random access memory array comprising:

• a semiconductor substrate;
• a plurality of non-volatile dynamic random access memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells including:
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate, wherein said storage capacitor further includes a plate formed in said layer of insulating material above said storage node and a connected contact;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a transfer transistor disposed between said storage node and said source diffusion region;
• and
• a floating gate formed in said layer of insulating material between said control electrode and said surface of said semiconductor substrate, said floating gate having a first layer disposed over said storage node and separated therefrom by said insulating material having a thickness that will allow electrons to tunnel between said storage node and said first layer for transferring a charge directly between said floating gate and said storage capacitor, and a second layer disposed at a greater distance from said surface of said semiconductor substrate than said first layer, said first layer being connected to said second layer.

A non-volatile dynamic random access memory array comprising:

• a semiconductor substrate;
• a plurality of non-volatile dynamic random access memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells including:
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a transfer transistor disposed between said storage node and said source diffusion region;
• a floating gate formed in said layer of insulating material between said control electrode and said surface of said semiconductor substrate, said floating gate having a first layer disposed over said storage node and separated therefrom by said insulating material having a thickness that will allow electrons to tunnel between said storage node and said first layer for transferring a charge directly between said floating gate and said storage capacitor, and a second layer disposed at a greater distance from said surface of said semiconductor substrate than said first layer, said first layer being connected to said second layer;
• and
• an erase gate formed in said layer of insulating material above said first layer of said floating gate.

A non-volatile dynamic random access memory array comprising:

• a semiconductor substrate;
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate, wherein said capacitor is directly electrically connected to ground;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a bit line directly electrically connected to said source diffusion region;
• a transfer transistor disposed between said storage node and said source diffusion region which is connected to the bit line to enable data to be transferred to and from the bit line to the storage capacitor;
• and
• a floating gate formed in said layer of insulating material between said control electrode and said surface of said semiconductor substrate, said floating gate having a first layer disposed over said storage node and separated therefrom by said insulating material having a thickness that will allow electrons to tunnel between said storage node and said first layer for transferring a charge directly between said floating gate and said storage capacitor, and a second layer disposed at a greater distance from said surface of said semiconductor substrate than said first layer, said first layer being connected to said second layer.

A non-volatile dynamic random access memory array comprising:

• a semiconductor substrate;
• a plurality of non-volatile dynamic random access memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells including:
• a layer of insulating material formed on a surface of said semiconductor substrate;
• a storage capacitor having a storage node formed in said semiconductor substrate, wherein said capacitor is directly electrically connected to ground;
• a control electrode formed on a surface of said insulating layer;
• a source diffusion region formed in said semiconductor substrate;
• a bit line directly electrically connected to said source diffusion region;
• a transfer transistor disposed between said storage node and said source diffusion region which is connected to the bit line to enable data to be transferred to and from the bit line to the storage capacitor;
• and
• a floating gate formed in said layer of insulating material between said control electrode and said surface of said semiconductor substrate, said floating gate having a first layer disposed over said storage node and separated therefrom by said insulating material having a thickness that will allow electrons to tunnel between said storage node and said first layer for transferring a charge directly between said floating gate and said storage capacitor, and a second layer disposed at a greater distance from said surface of said semiconductor substrate than said first layer, said first layer being connected to said second layer.